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LT1461CIS8-5#TRPBF

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Analog Devices Voltage References, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icslt1461cis8-5#trpbffactory-2.0.0extractor-text

Verified LT1461CIS8-5#TRPBF

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LT1461CIS8-5#TRPBF · SO-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 18-page datasheet
  • ✓distributor: lcsc C663904, digikey LT1461CIS8-5#TRPBFTR-ND, mouser 584-1461CIS8-5TRPBF
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-jy66p1w9/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lt1461cis8-5-trpbf.kicad_sym✓ lt1461cis8-5-trpbf.kicad_mod✓ lt1461cis8-5-trpbf.step
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Ray Publish 0.1.0 ccc658d 8d ago

LT1461CIS8-5#TRPBF

Analog Devices · Voltage References · SO-8

LT1461CIS8-5#TRPBF from Analog Devices, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DNC unconnected Do-not-connect pin; leave it unconnected.
2 VIN power_in Supply input; the datasheet requires (VOUT + 0.3V) ≤ VIN ≤ 20V, with a 20V absolute maximum.
3 SHDN input Shutdown input; pin low shuts off load current, and pin open or at or above 2.4V enables normal operation.
4 GND power_in Ground reference pin.
5 DNC unconnected Do-not-connect pin; leave it unconnected.
6 VOUT power_out Reference voltage output that delivers up to 50mA with a maximum 300mV dropout, and withstands a short to GND limited to 100mA.
7 DNC unconnected Do-not-connect pin; leave it unconnected.
8 DNC unconnected Do-not-connect pin; leave it unconnected.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SO-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Voltage accuracy (initial) VOUT -0.08 0.08 % C grade (LT1461CIS8); VIN, VOUT = 0.5V, Pin 3 = 2.4V, CL = 2µF 3
Output Voltage Temperature Coefficient 5 12 ppm/°C C grade (LT1461CIS8); l, over specified temperature range 3
Dropout Voltage VIN, VOUT 0.06 0.3 V VOUT Error = 0.1%, IOUT = 0mA 4
Dropout Voltage VIN, VOUT 0.13 0.4 V VOUT Error = 0.1%, IOUT = 1mA 4
Dropout Voltage VIN, VOUT 0.2 V VOUT Error = 0.1%, IOUT = 10mA 4
Dropout Voltage VIN, VOUT 1.5 2 V VOUT Error = 0.1%, IOUT = 50mA, I and C Grades Only; l 4
Shutdown Pin Logic High Input Voltage 2.4 V l 4
Logic Low Input Voltage 0.5 0.8 V l 4
Logic Low Input Current 4 µA Pin 3 = 0.8V; l 4
Supply Current IS 35 50 µA No load 4
Supply Current IS 70 µA No load; l 4
Shutdown Current IS(SHDN) 25 35 µA RL = 1k 4
Shutdown Current IS(SHDN) 55 µA RL = 1k; l 4
Output Voltage Noise, 0.1Hz ≤ f ≤ 10Hz 8 ppmP-P 0.1Hz ≤ f ≤ 10Hz 4
Output Voltage Noise, 10Hz ≤ f ≤ 1kHz 9.6 ppmRMS 10Hz ≤ f ≤ 1kHz 4
Long-Term Drift of Output Voltage, SO-8 Package 60 ppm/√kHr See Applications Information 4
Input Voltage VIN 20 V Absolute maximum 2
Operating Temperature Range TOP -40 125 °C Note 2 2
Storage Temperature Range TSTG -65 150 °C Note 3 2
Maximum Junction Temperature TJMAX 150 °C 2
Thermal Resistance, Junction-to-Ambient θJA 190 °C/W SO-8 package (Note 3) 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC to PC board stress because of the small amount of plastic 11

CAD (KiCad official)

  • Symbol: LT1461CIS8-5#TRPBF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: lt1461cis8-5-trpbf-etched.step / lt1461cis8-5-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt1461cis8-5-trpbf.step / lt1461cis8-5-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (18 pp, sha256 dcc2277edeb5e99d, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF