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LT1461CIS8-3.3#PBF
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Analog Devices Voltage References, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownLT1461CIS8-3.3#PBF
Analog Devices · Voltage References · SOIC-8
LT1461CIS8-3.3#PBF from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DNC | unconnected | Do not connect; the datasheet marks this pin DNC*, meaning it must be left unconnected. |
| 2 | VIN | power_in | Input supply; the datasheet requires (VOUT + 0.3V) ≤ VIN ≤ 20V, with an absolute maximum input voltage of 20V. |
| 3 | SHDN | input | Shutdown input; logic high is 2.4V minimum, logic low is 0.8V maximum, and the reference is operating with the pin open or at 2.4V or greater. |
| 4 | GND | power_in | Ground reference pin for the reference circuit. |
| 5 | DNC | unconnected | Do not connect; the datasheet marks this pin DNC*, meaning it must be left unconnected. |
| 6 | VOUT | power_out | Reference output; the part sources up to 50mA with 0 to 50mA load regulation specified, and an output capacitor of at least 1µF (2µF for loads above 1mA) is required for stability. |
| 7 | DNC | unconnected | Do not connect; the datasheet marks this pin DNC*, meaning it must be left unconnected. |
| 8 | DNC | unconnected | Do not connect; the datasheet marks this pin DNC*, meaning it must be left unconnected. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage initial accuracy | VOUT | -0.08 | 0.08 | % | LT1461CIS8, TA = 25°C | 3 | |
| Output Voltage Temperature Coefficient | 5 | 12 | ppm/°C | Industrial grade, -40°C to 85°C (l denotes over temperature range) | 3 | ||
| Line Regulation | 2 | 8 | ppm/V | (VOUT + 0.5V) ≤ VIN ≤ 20V | 4 | ||
| Load Regulation Sourcing | 12 | 30 | ppm/mA | VIN = VOUT + 2.5V, 0 ≤ IOUT ≤ 50mA | 4 | ||
| Dropout Voltage | VIN, VOUT | 0.06 | 0.3 | V | VOUT Error = 0.1%, IOUT = 0mA | 4 | |
| Dropout Voltage | VIN, VOUT | 0.13 | 0.4 | V | VOUT Error = 0.1%, IOUT = 1mA | 4 | |
| Dropout Voltage | VIN, VOUT | 0.2 | V | VOUT Error = 0.1%, IOUT = 10mA | 4 | ||
| Dropout Voltage | VIN, VOUT | 1.5 | 2 | V | VOUT Error = 0.1%, IOUT = 50mA, I and C Grades Only | 4 | |
| Shutdown Pin Logic High Input Voltage | 2.4 | V | 4 | ||||
| Logic High Input Current | 2 | 15 | µA | Pin 3 = 2.4V | 4 | ||
| Shutdown Pin Logic Low Input Voltage | 0.5 | 0.8 | V | 4 | |||
| Logic Low Input Current | 4 | µA | Pin 3 = 0.8V | 4 | |||
| Supply Current | 35 | 50 | µA | No Load | 4 | ||
| Shutdown Current | 25 | 35 | µA | RL = 1k | 4 | ||
| Output Current Short | 100 | mA | VOUT to GND | 4 | |||
| Input Voltage absolute maximum | VIN | 20 | V | 2 | |||
| Operating Temperature Range | TA | -40 | 125 | °C | Note 2 | 2 | |
| Storage Temperature Range | TSTG | -65 | 150 | °C | Note 3 | 2 | |
| Maximum Junction Temperature | TJMAX | 150 | °C | 2 | |||
| Specified Temperature Range Industrial | -40 | 85 | °C | Industrial grade (I suffix) | 2 | ||
| Thermal Resistance Junction-to-Ambient SO-8 | θJA | 190 | °C/W | Note 3 | 2 | ||
| Output Voltage Noise 0.1Hz to 10Hz | 8 | ppmP-P | 0.1Hz ≤ f ≤ 10Hz | 4 | |||
| Output Voltage Noise 10Hz to 1kHz | 9.6 | ppmRMS | 10Hz ≤ f ≤ 1kHz | 4 | |||
| Long-Term Drift of Output Voltage, SO-8 Package | 60 | ppm/√kHr | See Applications Information | 4 | |||
| Thermal Hysteresis | 75 | ppm | ΔT = -40°C to 85°C | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | to PC board stress because of the small amount of plastic | 11 |
CAD (KiCad official)
- Symbol:
LT1461CIS8-3.3#PBF - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
lt1461cis8-3-3-pbf-etched.step/lt1461cis8-3-3-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt1461cis8-3-3-pbf.step/lt1461cis8-3-3-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (18 pp, sha256
dcc2277edeb5e99d, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).