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LT1168CS8#PBF

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Analog Devices Instrumentation OpAmps, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Contents

README

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LT1168CS8#PBF

Analog Devices · Instrumentation OpAmps · SO-8

LT1168CS8#PBF from Analog Devices, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RG passive One of two gain-set resistor connections; a single external resistor sets gain as G = 1 + (49.4k/RG) for gains from 1 to 10,000.
2 -IN input Inverting input, ESD protected up to 13kV (human body) and specified with input bias current of 250pA max.
3 +IN input Non-inverting input, ESD protected up to 13kV (human body) and specified with input bias current of 250pA max.
4 -VS power_in Negative supply pin; the supply range is ±2.3V to ±18V.
5 REF input Reference input that sets the output reference; the reference voltage range is -VS + 1.6V to +VS - 1.6V.
6 OUTPUT output Amplifier output that can drive capacitive loads up to 1000pF in any gain configuration, with output current of 20mA min and 32mA typical.
7 +VS power_in Positive supply pin; the supply range is ±2.3V to ±18V.
8 RG passive Second gain-set resistor connection; the external gain resistor is connected between pins 1 and 8.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SO-8
Category Operational Amplifier/Comparator
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage -20 20 V 2
Differential Input Voltage -40 40 V Within the Supply Voltage 2
Input Voltage -20 20 V Equal to Supply Voltage 2
Input Current -20 20 mA Note 2 2
Storage Temperature Range -65 150 °C 2
Lead Temperature 300 °C Soldering, 10 sec 2
Maximum Junction Temperature TJMAX 150 °C 2
Operating Temperature Range -40 85 °C Note 4 2
Specified Temperature Range LT1168AC/LT1168C -40 85 °C Note 5 2
Thermal Resistance Junction-to-Ambient θJA 190 °C/W S8 package 2
Gain Error G 0.015 0.03 % G = 1 2
Gain Error G 0.05 0.5 % G = 10 (Note 7) 2
Gain Error G 0.05 0.6 % G = 100 (Note 7) 2
Gain Error G 0.08 0.6 % G = 1000 (Note 7) 2
Gain Nonlinearity 3 10 ppm VO = ±10V, G = 1 2
Gain Nonlinearity 15 25 ppm VO = ±10V, G = 10 and 100 2
Gain Nonlinearity 25 60 ppm VO = ±10V, G = 1000 2
Gain Nonlinearity 5 20 ppm VO = ±10V, G = 1, RL = 2k 2
Gain Nonlinearity 30 60 ppm VO = ±10V, G = 10 and 100, RL = 2k 2
Gain Nonlinearity 50 90 ppm VO = ±10V, G = 1000, RL = 2k 2
Input Offset Voltage VOSI 20 60 µV G = 1000, VS = ±5V to ±15V 2
Output Offset Voltage VOSO 50 300 µV G = 1, VS = ±5V to ±15V 2
Input Offset Current IOS 60 450 pA 2
Input Bias Current IB 80 500 pA 2
Input Noise Voltage Density, RTI en 10 15 nV/√Hz fO = 1kHz 2
Output Noise Voltage Density, RTI 165 220 nV/√Hz fO = 1kHz (Note 9) 2
Input Resistance RIN 200 1250 GΩ VIN = ±10V 2
Gain Error G 0.012 0.04 % G = 1, 0°C ≤ TA ≤ 70°C 3
Gain Error G 0.5 1.6 % G = 10 (Note 7), 0°C ≤ TA ≤ 70°C 3
Gain Error G 0.55 1.7 % G = 100 (Note 7), 0°C ≤ TA ≤ 70°C 3
Gain Error G 0.6 1.8 % G = 1000 (Note 7), 0°C ≤ TA ≤ 70°C 3
Gain Nonlinearity 3 20 ppm VOUT = ±10V, G = 1, 0°C ≤ TA ≤ 70°C 3
Gain Nonlinearity 10 35 ppm VOUT = ±10V, G = 10 and 100, 0°C ≤ TA ≤ 70°C 3
Gain Nonlinearity 30 80 ppm VOUT = ±10V, G = 1000, 0°C ≤ TA ≤ 70°C 3
Gain vs Temperature ∆G/∆T 100 200 ppm/°C G < 1000 (Note 7), 0°C ≤ TA ≤ 70°C 3
Common Mode Rejection Ratio CMRR 85 95 dB G = 1, 1k Source Imbalance, VCM = 0V to ±10V 3
Common Mode Rejection Ratio CMRR 100 115 dB G = 10, 1k Source Imbalance, VCM = 0V to ±10V 3
Common Mode Rejection Ratio CMRR 110 135 dB G = 100, 1k Source Imbalance, VCM = 0V to ±10V 3
Common Mode Rejection Ratio CMRR 120 140 dB G = 1000, 1k Source Imbalance, VCM = 0V to ±10V 3
Power Supply Rejection Ratio PSRR 100 108 dB G = 1, VS = ±2.3V to ±18V 3
Power Supply Rejection Ratio PSRR 118 128 dB G = 10, VS = ±2.3V to ±18V 3
Power Supply Rejection Ratio PSRR 126 145 dB G = 100, VS = ±2.3V to ±18V 3
Power Supply Rejection Ratio PSRR 130 150 dB G = 1000, VS = ±2.3V to ±18V 3
Supply Current IS 350 530 µA VS = ±2.3V to ±18V 3
Output Current IOUT 20 32 mA 3
Slew Rate SR 0.3 0.5 V/µs G = 1, VOUT = ±10V 3
Input Offset Voltage VOSI 23 80 µV VS = ±5V to ±15V, 0°C ≤ TA ≤ 70°C 4
Output Offset Voltage VOSO 70 500 µV VS = ±5V to ±15V, 0°C ≤ TA ≤ 70°C 4
Input Offset Drift (RTI) VOSI/T 0.06 0.4 µV/°C 0°C ≤ TA ≤ 70°C 4
Output Offset Drift VOSO/T 0.8 4 µV/°C 0°C ≤ TA ≤ 70°C 4
Input Offset Current IOS 120 550 pA 0°C ≤ TA ≤ 70°C 4
Input Bias Current IB 105 600 pA 0°C ≤ TA ≤ 70°C 4
Output Current IOUT 16 25 mA 0°C ≤ TA ≤ 70°C 4
Slew Rate SR 0.25 0.48 V/µs G = 1, VOUT = ±10V, 0°C ≤ TA ≤ 70°C 4
Supply Current IS 390 615 µA VS = ±2.3V to ±18V, 0°C ≤ TA ≤ 70°C 4
Common Mode Rejection Ratio CMRR 83 92 dB G = 1, 1k Source Imbalance, VCM = 0V to ±10V, 0°C ≤ TA ≤ 70°C 4
Voltage Gain Error Reference to Output AVREF -0.0001 1 0.0001 VREF 3
Small-Signal Bandwidth BW 400 kHz G = 1 3
Small-Signal Bandwidth BW 200 kHz G = 10 3
Settling Time to 0.01% 30 µs 10V Step, G = 1 to 100 3

CAD (KiCad official)

  • Symbol: LT1168CS8#PBF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: lt1168cs8-pbf-etched.step / lt1168cs8-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt1168cs8-pbf.step / lt1168cs8-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (20 pp, sha256 601691d8214d1343, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF