LT1167CS8#TRPBF from Analog Devices, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RG	passive	Gain-setting resistor terminal; one resistor between pins 1 and 8 sets G = 1 + (49.4k/RG) over a gain range of 1 to 10,000.
2	-IN	input	Inverting input of the instrumentation amplifier, ESD protected, with input voltage range of -VS + 1.9V to +VS - 1.4V (VS = ±5V to ±18V) and a differential input voltage limit of ±40V.
3	+IN	input	Non-inverting input of the instrumentation amplifier, ESD protected, with input voltage range of -VS + 1.9V to +VS - 1.4V (VS = ±5V to ±18V) and 350pA maximum input bias current (LT1167A grade).
4	-VS	power_in	Negative supply pin; supply range is ±2.3V to ±18V with an absolute maximum of ±20V.
5	REF	input	Reference input that sets the output voltage level relative to which the output swings.
6	OUTPUT	output	Amplifier output, short-circuit protected indefinitely and able to drive capacitive loads up to 1000pF and loads as low as 2k.
7	+VS	power_in	Positive supply pin; supply range is ±2.3V to ±18V with an absolute maximum of ±20V and 1.3mA maximum supply current.
8	RG	passive	Gain-setting resistor terminal; one resistor between pins 8 and 1 sets G = 1 + (49.4k/RG) over a gain range of 1 to 10,000.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SO-8
Category	Operational Amplifier/Comparator
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage		-20		20	V		2
Differential Input Voltage		-40		40	V	Within the supply voltage	2
Input Voltage		-20		20	V	Equal to supply voltage	2
Input Current		-20		20	mA	Note 3	2
Operating Temperature Range		-40		85	°C		2
Specified Temperature Range (LT1167C)		0		70	°C	LT1167C	2
Storage Temperature Range		-65		150	°C		2
Lead Temperature (Soldering, 10 sec)				300	°C	Soldering, 10 sec	2
Maximum Junction Temperature	TJMAX			150	°C	S8 package	2
Thermal Resistance, Junction to Ambient	θJA		190		°C/W	S8 package	2
Gain Error			0.015	0.03	%	G = 1	3
Gain Error			0.02	0.1	%	G = 10 (Note 2)	3
Gain Error			0.03	0.1	%	G = 100 (Note 2)	3
Gain Error			0.04	0.1	%	G = 1000 (Note 2)	3
Gain Nonlinearity			1.5	10	ppm	VO = ±10V, G = 1	3
Gain Nonlinearity			3	15	ppm	VO = ±10V, G = 10 and 100	3
Gain Nonlinearity			20	60	ppm	VO = ±10V, G = 1000	3
Input Offset Voltage	VOSI		20	60	μV	G = 1000, VS = ±5V to ±15V	3
Output Offset Voltage	VOSO		50	300	μV	G = 1, VS = ±5V to ±15V	3
Input Offset Current	IOS		100	450	pA		3
Input Bias Current	IB		80	500	pA		3
Input Noise Voltage Density	eni		7.5	12	nV/√Hz	fO = 1kHz	3
Output Noise Voltage Density	eno		67	90	nV/√Hz	fO = 1kHz (Note 3)	3
Input Resistance	RIN	200	1000		GΩ	VIN = ±10V	3
Common Mode Rejection Ratio	CMRR	85	95		dB	1k Source Imbalance, VCM = 0V to ±10V, G = 1	3
Common Mode Rejection Ratio	CMRR	100	115		dB	1k Source Imbalance, VCM = 0V to ±10V, G = 10	3
Common Mode Rejection Ratio	CMRR	110	125		dB	1k Source Imbalance, VCM = 0V to ±10V, G = 100	3
Common Mode Rejection Ratio	CMRR	120	140		dB	1k Source Imbalance, VCM = 0V to ±10V, G = 1000	3
Power Supply Rejection Ratio	PSRR	100	120		dB	VS = ±2.3V to ±18V, G = 1	3
Power Supply Rejection Ratio	PSRR	120	135		dB	VS = ±2.3V to ±18V, G = 10	3
Power Supply Rejection Ratio	PSRR	126	140		dB	VS = ±2.3V to ±18V, G = 100	3
Power Supply Rejection Ratio	PSRR	130	150		dB	VS = ±2.3V to ±18V, G = 1000	3
Supply Current	IS		0.9	1.3	mA	VS = ±2.3V to ±18V	3
Slew Rate	SR	0.75	1.2		V/μs	G = 1, VOUT = ±10V	4
Gain Error			0.012	0.04	%	G = 1, 0°C ≤ TA ≤ 70°C	4
Gain Error			0.1	0.33	%	G = 10 (Note 2), 0°C ≤ TA ≤ 70°C	4
Gain Error			0.12	0.33	%	G = 100 (Note 2), 0°C ≤ TA ≤ 70°C	4
Gain Error			0.14	0.35	%	G = 1000 (Note 2), 0°C ≤ TA ≤ 70°C	4
Gain Nonlinearity			3	15	ppm	VOUT = ±10V, G = 1, 0°C ≤ TA ≤ 70°C	4
Gain Nonlinearity			4	20	ppm	VOUT = ±10V, G = 10 and 100, 0°C ≤ TA ≤ 70°C	4
Gain Nonlinearity			25	80	ppm	VOUT = ±10V, G = 1000, 0°C ≤ TA ≤ 70°C	4
Gain vs Temperature	G/T		20	50	ppm/°C	G < 1000 (Note 2)	4
Input Offset Voltage	VOSI		23	80	μV	VS = ±5V to ±15V, 0°C ≤ TA ≤ 70°C	4
Output Offset Voltage	VOSO		70	500	μV	VS = ±5V to ±15V, 0°C ≤ TA ≤ 70°C	4
Input Offset Drift	VOSI/T		0.06	0.4	μV/°C	(Note 8) (Note 3)	4
Output Offset Drift	VOSO/T		0.8	4	μV/°C	(Note 3)	4
Input Offset Current	IOS		120	550	pA	0°C ≤ TA ≤ 70°C	4
Input Bias Current	IB		105	600	pA	0°C ≤ TA ≤ 70°C	4
Common Mode Rejection Ratio	CMRR	83	92		dB	1k Source Imbalance, VCM = 0V to ±10V, G = 1, 0°C ≤ TA ≤ 70°C	4
Common Mode Rejection Ratio	CMRR	97	110		dB	1k Source Imbalance, VCM = 0V to ±10V, G = 10, 0°C ≤ TA ≤ 70°C	4
Common Mode Rejection Ratio	CMRR	113	120		dB	1k Source Imbalance, VCM = 0V to ±10V, G = 100, 0°C ≤ TA ≤ 70°C	4
Common Mode Rejection Ratio	CMRR	114	135		dB	1k Source Imbalance, VCM = 0V to ±10V, G = 1000, 0°C ≤ TA ≤ 70°C	4
Power Supply Rejection Ratio	PSRR	98	115		dB	VS = ±2.3V to ±18V, G = 1, 0°C ≤ TA ≤ 70°C	5
Power Supply Rejection Ratio	PSRR	118	130		dB	VS = ±2.3V to ±18V, G = 10, 0°C ≤ TA ≤ 70°C	5
Power Supply Rejection Ratio	PSRR	124	135		dB	VS = ±2.3V to ±18V, G = 100, 0°C ≤ TA ≤ 70°C	5
Power Supply Rejection Ratio	PSRR	126	145		dB	VS = ±2.3V to ±18V, G = 1000, 0°C ≤ TA ≤ 70°C	5
Supply Current	IS		1	1.5	mA	VS = ±2.3V to ±18V, 0°C ≤ TA ≤ 70°C	5
Output Current	IOUT	16	21		mA	0°C ≤ TA ≤ 70°C	5
Slew Rate	SR	0.65	1.1		V/μs	G = 1, VOUT = ±10V, 0°C ≤ TA ≤ 70°C	5

CAD (KiCad official)

Symbol: LT1167CS8#TRPBF
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SO-8 (KiCad packages3D, STEP)
3D model files: lt1167cs8-trpbf-etched.step / lt1167cs8-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt1167cs8-trpbf.step / lt1167cs8-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (22 pp, sha256 4c899f773e4f70ec, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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LT1167CS8#TRPBF

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