LT1058CN#PBF from Analog Devices, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUTPUT A	output	Amplifier A output, swings at least ±12V into 2k with ±15V supplies and is short-circuit protected indefinitely.
2	-IN A	input	Amplifier A inverting JFET input, with differential input voltage limited to ±40V and input voltage to ±20V.
3	+IN A	input	Amplifier A non-inverting JFET input, with differential input voltage limited to ±40V and input voltage to ±20V.
4	V+	power_in	Positive supply, shared by all four amplifiers, with a maximum supply voltage of ±20V.
5	+IN B	input	Amplifier B non-inverting JFET input, with differential input voltage limited to ±40V and input voltage to ±20V.
6	-IN B	input	Amplifier B inverting JFET input, with differential input voltage limited to ±40V and input voltage to ±20V.
7	OUTPUT B	output	Amplifier B output, swings at least ±12V into 2k with ±15V supplies and is short-circuit protected indefinitely.
8	OUTPUT C	output	Amplifier C output, swings at least ±12V into 2k with ±15V supplies and is short-circuit protected indefinitely.
9	-IN C	input	Amplifier C inverting JFET input, with differential input voltage limited to ±40V and input voltage to ±20V.
10	+IN C	input	Amplifier C non-inverting JFET input, with differential input voltage limited to ±40V and input voltage to ±20V.
11	V-	power_in	Negative supply, shared by all four amplifiers, with a maximum supply voltage of ±20V.
12	+IN D	input	Amplifier D non-inverting JFET input, with differential input voltage limited to ±40V and input voltage to ±20V.
13	-IN D	input	Amplifier D inverting JFET input, with differential input voltage limited to ±40V and input voltage to ±20V.
14	OUTPUT D	output	Amplifier D output, swings at least ±12V into 2k with ±15V supplies and is short-circuit protected indefinitely.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	PDIP-14
Category	Amplifiers
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input Offset Voltage (LT1058C)	VOS		250	1000	µV	VS=±15V, TA=25°C, VCM=0V	3
Input Offset Current	IOS		4	50	pA	Fully Warmed Up	3
Input Bias Current	IB		7	75	pA	Fully Warmed Up (typ ±7, max ±75)	3
Input Noise Voltage Density	en		14	24	nV/√Hz	fO = 1kHz (Note 3)	3
Input Noise Current Density	in		1.8	6	fA/√Hz	fO = 10Hz, 1kHz (Note 4)	3
Large-Signal Voltage Gain	AVOL	100	300		V/mV	VO = ±10V, RL = 2k	3
Large-Signal Voltage Gain	AVOL	80	220		V/mV	VO = ±10V, RL = 1k	3
Input Voltage Range		10.5	14.3		V	min ±10.5; typ 14.3 / -11.5	3
Common Mode Rejection Ratio (LT1058)	CMRR	80	96		dB		3
Power Supply Rejection Ratio	PSRR	86	102		dB	VS = ±10V to ±18V	3
Output Voltage Swing	VOUT	12	13		V	RL = 2k (±12 min, ±13 typ)	3
Slew Rate	SR	8	13		V/µs		3
Gain-Bandwidth Product	GBW	3	5		MHz	f = 1MHz (Note 6)	3
Supply Current Per Amplifier	IS		1.7	2.8	mA		3
Input Offset Voltage (LT1058C, 0°C to 70°C)	VOS		400	1800	µV	0°C ≤ TA ≤ 70°C	4
Average Temperature Coefficient of Input Offset Voltage (LT1058 N Package)			5	22	µV/°C	0°C ≤ TA ≤ 70°C (Note 5)	4
Input Offset Current	IOS		20	250	pA	Warmed Up, TA = 70°C	4
Input Bias Current	IB		60	350	pA	Warmed Up, TA = 70°C (typ ±60, max ±350)	4
Large-Signal Voltage Gain	AVOL	50	200		V/mV	VO = ±10V, RL = 2k, 0°C to 70°C	4
Common Mode Rejection Ratio	CMRR	80	96		dB	VCM = ±10.4V, 0°C to 70°C	4
Power Supply Rejection Ratio	PSRR	84	100		dB	VS = ±10V to ±18V, 0°C to 70°C	4
Output Voltage Swing	VOUT	12	12.8		V	RL = 2k, 0°C to 70°C (±12 min, ±12.8 typ)	4
Supply Voltage		-20		20	V	±20V	2
Differential Input Voltage		-40		40	V	±40V	2
Input Voltage		-20		20	V	±20V	2
Storage Temperature Range		-65		150	°C		2
Lead Temperature (Soldering, 10 sec)				300	°C		2
Operating Temperature Range (LT1058C)		0		70	°C		2
Junction Temperature (N14 package)	TJMAX			125	°C	N14 PACKAGE	2
Thermal Resistance Junction to Ambient (N14 package)	θJA		130		°C/W	N14 PACKAGE	2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS	14

CAD (KiCad official)

Symbol: LT1058CN#PBF
Footprint: Package_DIP:DIP-14_W7.62mm
3D model: PDIP-14 (KiCad packages3D, STEP)
3D model files: lt1058cn-pbf-etched.step / lt1058cn-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt1058cn-pbf.step / lt1058cn-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (16 pp, sha256 1cfc1e91ea879c76, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LT1058CN#PBF

Verified LT1058CN#PBF

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README