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LT1007CS8#PBF

Analog Devices · Operational Amplifier · SO-8

LT1007CS8#PBF from Analog Devices, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOS TRIM passive Offset voltage null terminal, used with a 10kΩ potentiometer (wiper to V+) for an adjustment range of approximately ±2.5mV.
2 -IN input Inverting input, protected by back-to-back diodes so differential input current should be limited to 25mA if the differential voltage exceeds ±0.7V.
3 +IN input Noninverting input, with input voltage range of ±11.0V minimum at VS = ±15V and absolute maximum equal to the supply voltage.
4 V- power_in Negative supply, with total supply voltage rating up to ±22V maximum.
5 NC unconnected No internal connection.
6 OUT output Amplifier output with indefinite short-circuit duration and a typical swing of ±13.5V into 2kΩ at VS = ±15V.
7 V+ power_in Positive supply, with total supply voltage rating up to ±22V maximum.
8 VOS TRIM passive Offset voltage null terminal, used with a 10kΩ potentiometer (wiper to V+) for an adjustment range of approximately ±2.5mV.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SO-8
Category Operational Amplifier/Comparator
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage 22 V 2
Differential Input Current 25 mA Note 9 2
Storage Temperature Range -65 150 °C 2
Lead Temperature (Soldering) 300 °C 10 sec. 2
Operating Temperature Range LT1007C 0 70 °C LT1007/LT1037AC, C 2
Input Offset Voltage VOS 20 60 µV 2
Long Term Input Offset Voltage Stability ∆VOS 0.2 1 µV/Mo 2
Input Offset Current IOS 12 50 nA 2
Input Bias Current IB 15 55 nA 2
Input Noise Voltage 0.1Hz to 10Hz en 0.06 0.13 µVP-P 0.1Hz to 10Hz (Notes 4, 6) 2
Input Noise Voltage Density en 2.8 4.5 nV/√Hz fO = 10Hz (Notes 4, 5) 2
Input Noise Voltage Density en 2.5 3.8 nV/√Hz fO = 1000Hz (Note 4) 2
Input Noise Current Density in 1.5 4 pA/√Hz fO = 10Hz (Notes 4, 7) 2
Input Noise Current Density in 0.4 0.6 pA/√Hz fO = 1000Hz (Notes 4, 7) 2
Input Voltage Range 11 12.5 V 3
Common Mode Rejection Ratio CMRR 110 126 dB VCM = ±11V 3
Power Supply Rejection Ratio PSRR 106 126 dB VS = ±4V to ±18V 3
Large-Signal Voltage Gain AVOL 5 20 V/µV RL ≥ 2k, VO = ±12V 3
Large-Signal Voltage Gain AVOL 3.5 16 V/µV RL ≥ 1k, VO = ±10V 3
Large-Signal Voltage Gain AVOL 2 12 V/µV RL ≥ 600Ω, VO = ±10V 3
Maximum Output Voltage Swing VOUT 12.5 13.5 V RL ≥ 2k 3
Maximum Output Voltage Swing VOUT 10.5 12.5 V RL ≥ 600Ω 3
Slew Rate LT1007 SR 1.7 2.5 V/µs RL ≥ 2k 3
Gain Bandwidth Product LT1007 GBW 5 8 MHz fO = 100kHz (Note 8) 3
Open-Loop Output Resistance ZO 70 Ω VO = 0V, IO = 0 3
Power Dissipation LT1007 PD 80 140 mW 3
Input Offset Voltage over 0°C to 70°C VOS 35 110 µV 0°C ≤ TA ≤ 70°C 3
Average Input Offset Drift ∆VOS 0.3 1 µV/°C 0°C ≤ TA ≤ 70°C (Note 10) 3
Input Offset Current over 0°C to 70°C IOS 15 70 nA 0°C ≤ TA ≤ 70°C 3
Input Bias Current over 0°C to 70°C IB 20 75 nA 0°C ≤ TA ≤ 70°C 3
Input Voltage Range over 0°C to 70°C 10.5 11.8 V 0°C ≤ TA ≤ 70°C 3
Common Mode Rejection Ratio over 0°C to 70°C CMRR 106 120 dB VCM = ±10.5V, 0°C ≤ TA ≤ 70°C 3
Power Supply Rejection Ratio over 0°C to 70°C PSRR 102 120 dB VS = ±4.5V to ±18V, 0°C ≤ TA ≤ 70°C 3
Large-Signal Voltage Gain over 0°C to 70°C AVOL 2.5 18 V/µV RL ≥ 2k, VO = ±10V, 0°C ≤ TA ≤ 70°C 3
Large-Signal Voltage Gain over 0°C to 70°C AVOL 2 14 V/µV RL ≥ 1k, VO = ±10V, 0°C ≤ TA ≤ 70°C 3
Maximum Output Voltage Swing over 0°C to 70°C VOUT 12 13.6 V RL ≥ 2k, 0°C ≤ TA ≤ 70°C 3
Power Dissipation over 0°C to 70°C PD 90 160 mW 0°C ≤ TA ≤ 70°C 3
Junction Temperature Maximum TJMAX 150 °C S8 package 2
Thermal Resistance Junction to Ambient θJA 190 °C/W S8 package 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE (1.143, 1.651) OR TIN PLATE LEADS 14

CAD (KiCad official)

  • Symbol: LT1007CS8#PBF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: lt1007cs8-pbf-etched.step / lt1007cs8-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt1007cs8-pbf.step / lt1007cs8-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (16 pp, sha256 2b7b412f54486c64, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF