component

LT1001CS8#TRPBF

Public Made by Adom

by adom

Analog Devices Precision OpAmps, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentamplifierslt1001cs8#trpbffactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 6d ago
viewers lt1001cs8-trpbf: viewers · Ray 6d ago
lt1001cs8-trpbf-etched.glb Publish 0.1.0 · Ray 6d ago
lt1001cs8-trpbf-etched.step lt1001cs8-trpbf: factory component page (tier=mfr) · Ray 6d ago
lt1001cs8-trpbf-hero.glb lt1001cs8-trpbf: hero GLB from the etched model (keeps the MPN mark) · Ray 6d ago
lt1001cs8-trpbf-hero.overlay.json Publish 0.1.0 · Ray 6d ago
lt1001cs8-trpbf.glb Publish 0.1.0 · Ray 6d ago
lt1001cs8-trpbf.kicad_mod Publish 0.1.0 · Ray 6d ago
lt1001cs8-trpbf.kicad_sym Publish 0.1.0 · Ray 6d ago
lt1001cs8-trpbf.lbr Publish 0.1.0 · Ray 6d ago
lt1001cs8-trpbf.step Publish 0.1.0 · Ray 6d ago
package.json Publish 0.1.0 · Ray 6d ago
page.json Set visibility: public · Ray 6d ago
README.md Publish 0.1.0 · Ray 6d ago

LT1001CS8#TRPBF

Analog Devices · Precision OpAmps · SO-8

LT1001CS8#TRPBF from Analog Devices, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOS TRIM passive Offset adjust terminal for an external 10k or 20k nulling potentiometer giving approximately ±2.5mV adjustment range.
2 -IN input Inverting input; differential input voltage is limited to ±30V and input voltage to ±22V.
3 +IN input Non-inverting input; differential input voltage is limited to ±30V and input voltage to ±22V.
4 V- power_in Negative supply; specified for ±3V to ±18V supplies with an absolute maximum total supply of ±22V.
5 NC unconnected No internal connection.
6 OUT output Amplifier output with indefinite short-circuit duration and a guaranteed swing of ±13V minimum into RL ≥ 2kΩ (0°C to 70°C).
7 V+ power_in Positive supply; specified for ±3V to ±18V supplies with an absolute maximum total supply of ±22V.
8 VOS TRIM passive Offset adjust terminal for an external 10k or 20k nulling potentiometer giving approximately ±2.5mV adjustment range.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SO-8
Category Amplifiers
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage -22 22 V Printed as ±22V 2
Differential Input Voltage -30 30 V Printed as ±30V 2
Input Voltage -22 22 V Printed as ±22V 2
Operating Temperature Range LT1001AC/LT1001C 0 125 °C LT1001AC/LT1001C 2
Storage Temperature -65 150 °C All devices 2
Lead Temperature (Soldering, 10 sec) 300 °C Soldering, 10 sec. 2
Maximum Junction Temperature TJMAX 150 °C 2
Thermal Resistance Junction-to-Ambient (S package) θJA 150 °C/W S package 2
Thermal Resistance Junction-to-Case θjc 45 °C/W 2
Input Offset Voltage VOS 18 60 µV LT1001M/LT1001C, TA = 25°C 2
Long Term Input Offset Voltage Stability ΔVOS/Δtime 0.3 1.5 µV/month Notes 3 and 4 2
Input Offset Current IOS 0.4 3.8 nA TA = 25°C 2
Input Bias Current Ib 0.7 4 nA TA = 25°C, magnitude (±) 2
Input Noise Voltage 0.1Hz to 10Hz en 0.3 0.6 µVp-p Note 3 2
Input Noise Voltage Density en 10.5 18 nV√Hz fO = 10Hz (Note 6) 2
Input Noise Voltage Density en 9.8 11 nV√Hz fO = 1000Hz (Note 3) 2
Large Signal Voltage Gain AVOL 400 800 V/mV RL ≥ 2kΩ, VO = ±12V 2
Large Signal Voltage Gain AVOL 250 500 V/mV RL ≥ 1kΩ, VO = ±10V 2
Common Mode Rejection Ratio CMRR 110 126 dB VCM = ±13V 2
Power Supply Rejection Ratio PSRR 106 123 dB VS = ±3V to ±18V 2
Input Resistance Differential Mode Rin 15 80 MΩ Differential Mode 2
Input Offset Voltage VOS 30 110 µV 0°C ≤ TA ≤ 70°C (LT1001C) 3
Average Offset Voltage Drift ΔVOS/ΔTemp 0.3 1 µV/°C 0°C ≤ TA ≤ 70°C (LT1001C) 3
Input Offset Current IOS 0.6 5.3 nA 0°C ≤ TA ≤ 70°C (LT1001C) 3
Input Bias Current IB 1 5.5 nA 0°C ≤ TA ≤ 70°C (LT1001C), magnitude (±) 3
Large Signal Voltage Gain AVOL 250 750 V/mV RL ≥ 2kΩ, VO = ±10V, 0°C ≤ TA ≤ 70°C (LT1001C) 3
Common Mode Rejection Ratio CMRR 106 123 dB VCM = ±13V, 0°C ≤ TA ≤ 70°C (LT1001C) 3
Power Supply Rejection Ratio PSRR 103 120 dB VS = ±3V to ±18V, 0°C ≤ TA ≤ 70°C (LT1001C) 3
Output Voltage Swing VOUT 12.5 13.8 V RL ≥ 2kΩ, 0°C ≤ TA ≤ 70°C (LT1001C), printed ± 3
Power Dissipation Pd 55 90 mW No load, 0°C ≤ TA ≤ 70°C (LT1001C) 3
Slew Rate SR 0.1 0.25 V/µs RL ≥ 2kΩ (Note 5) 3
Gain-Bandwidth Product GBW 0.4 0.8 MHz Note 5 3
Power Dissipation Pd 48 80 mW No load (LT1001C) 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE (1.143, 1.651) OR TIN PLATE LEADS 14

CAD (KiCad official)

  • Symbol: LT1001CS8#TRPBF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: lt1001cs8-trpbf-etched.step / lt1001cs8-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt1001cs8-trpbf.step / lt1001cs8-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (16 pp, sha256 6b3481afd5a39a91, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF