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LT1001CS8#PBF

Analog Devices · Precision OpAmps · SO-8

LT1001CS8#PBF from Analog Devices, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOS TRIM passive Offset adjust terminal; a 10k or 20k potentiometer between pins 1 and 8 gives about ±2.5mV of adjustment range without degrading drift.
2 -IN input Inverting input; differential input voltage is limited to ±30V and input voltage to ±22V (absolute maximum).
3 +IN input Non-inverting input; differential input voltage is limited to ±30V and input voltage to ±22V (absolute maximum).
4 V- power_in Negative supply; specified for ±3V to ±18V supplies, with an absolute maximum of ±22V.
5 NC unconnected No internal connection.
6 OUT output Amplifier output; output short-circuit duration is indefinite, with voltage gain guaranteed at 10mA of load current.
7 V+ power_in Positive supply; specified for ±3V to ±18V supplies, with an absolute maximum of ±22V.
8 VOS TRIM passive Offset adjust terminal; a 10k or 20k potentiometer between pins 1 and 8 gives about ±2.5mV of adjustment range without degrading drift.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SO-8
Category Amplifiers
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Offset Voltage VOS 18 60 µV Note 2 2
Long Term Input Offset Voltage Stability ∆VOS/∆Time 0.3 1.5 µV/month Notes 3 and 4 2
Input Offset Current IOS 0.4 3.8 nA 2
Input Bias Current Ib 0.7 4 nA 2
Input Noise Voltage 0.1Hz to 10Hz en 0.3 0.6 µVp-p 0.1Hz to 10Hz (Note 3) 2
Input Noise Voltage Density en 10.5 18 nV√Hz fO = 10Hz (Note 6) 2
Input Noise Voltage Density en 9.8 11 nV√Hz fO = 1000Hz (Note 3) 2
Large Signal Voltage Gain AVOL 400 800 V/mV RL ≥ 2kΩ, VO = ±12V 2
Large Signal Voltage Gain AVOL 250 500 V/mV RL ≥ 1kΩ VO = ±10V 2
Common Mode Rejection Ratio CMRR 110 126 dB VCM = ±13V 2
Power Supply Rejection Ratio PSRR 106 123 dB VS = ±3V to ±18V 2
Input Resistance Differential Mode Rin 15 80 MΩ Differential Mode 2
Input Offset Voltage VOS 30 110 µV ● VS = ±15V, -55°C ≤ TA ≤ 125°C 3
Average Offset Voltage Drift ∆VOS/∆Temp 0.3 1 µV/°C ● VS = ±15V, -55°C ≤ TA ≤ 125°C 3
Input Offset Current IOS 0.6 5.3 nA ● VS = ±15V, -55°C ≤ TA ≤ 125°C 3
Input Bias Current IB 1 5.5 nA ● VS = ±15V, -55°C ≤ TA ≤ 125°C 3
Large Signal Voltage Gain AVOL 250 750 V/mV ● VS = ±15V, -55°C ≤ TA ≤ 125°C, RL ≥ 2kΩ, VO = ±10V 3
Common Mode Rejection Ratio CMRR 106 123 dB ● VS = ±15V, -55°C ≤ TA ≤ 125°C, VCM = ±13V 3
Power Supply Rejection Ratio PSRR 103 120 dB ● VS = ±15V, -55°C ≤ TA ≤ 125°C, VS = ±3V to ±18V 3
Input Voltage Range 13 14 V ● VS = ±15V, -55°C ≤ TA ≤ 125°C 3
Output Voltage Swing VOUT 12.5 13.8 V ● VS = ±15V, -55°C ≤ TA ≤ 125°C, RL ≥ 2kΩ 3
Power Dissipation Pd 55 90 mW ● VS = ±15V, -55°C ≤ TA ≤ 125°C, No load 3
Maximum Output Voltage Swing VOUT 13 14 V 0°C ≤ TA ≤ 70°C, RL ≥ 2kΩ 3
Maximum Output Voltage Swing VOUT 12 13.5 V 0°C ≤ TA ≤ 70°C, RL ≥ 1kΩ 3
Slew Rate SR 0.1 0.25 V/µs RL ≥ 2kΩ (Note 5) 3
Gain-Bandwidth Product GBW 0.4 0.8 MHz (Note 5) 3
Power Dissipation Pd 48 80 mW 0°C ≤ TA ≤ 70°C, No load 3
Power Dissipation Pd 4 8 mW No load, VS = ±3V 3
Supply Voltage 22 V 2
Differential Input Voltage 30 V 2
Input Voltage 22 V 2
Storage Temperature Range -65 150 °C All devices 2
Lead Temperature (Soldering, 10 sec.) 300 °C Soldering, 10 sec. 2
Operating Temperature Range 0 125 °C LT1001AC/LT1001C 2
Thermal Resistance Junction to Ambient θJA 150 °C/W S package, TJMAX = 150°C 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE (1.143, 1.651) OR TIN PLATE LEADS 14

CAD (KiCad official)

  • Symbol: LT1001CS8#PBF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: lt1001cs8-pbf-etched.step / lt1001cs8-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt1001cs8-pbf.step / lt1001cs8-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (16 pp, sha256 6b3481afd5a39a91, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF