# LSI1012LT1G

**LRC** · MOSFETs · SOT-23

LSI1012LT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Gate | input | Gate of the N-channel 1.8-V MOSFET, rated for a gate-source voltage (VGS) of 6 V maximum per the absolute maximum ratings, with gate-source ESD protection and a gate threshold of 0.45 V to 0.9 V. |
| 2 | Source | passive | Source of the N-channel MOSFET; continuous source (diode conduction) current is limited to 275 mA for 5 s and 250 mA in steady state. |
| 3 | Drain | passive | Drain of the N-channel MOSFET; drain-source voltage is rated at 20 V maximum, with continuous drain current of 600 mA at TA = 25°C for 5 s and 500 mA in steady state. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## CAD (KiCad official)

- Symbol: `LSI1012LT1G`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `lsi1012lt1g-etched.step` / `lsi1012lt1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lsi1012lt1g.step` / `lsi1012lt1g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [LRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588880669908459520) (6 pp, sha256 `37d6304fcc480fe1`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lsi1012lt1g-datasheet.pdf)