component
LS7083N-S
Public Made by Adomby adom
LSI/CSI Interface - Specialized, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LS7083N-S
LSI/CSI · Interface - Specialized · SOIC-8
LS7083N-S from LSI/CSI, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RBIAS | passive | External resistor connected between this pin and VSS sets the output clock pulse width TOW, which must be less than or equal to the A, B pulse separation (TOW ≤ TPS); RB range 2K to 10M ohm. |
| 2 | VDD | power_in | Positive supply terminal, +3V to +12V operation (VDD - VSS), absolute maximum 16V. |
| 3 | VSS | power_in | Negative supply terminal (ground). |
| 4 | A | input | Quadrature clock input A with a filter circuit to validate input logic level and eliminate encoder dither; logic 0 max 0.25VDD, logic 1 min 0.7VDD. |
| 5 | B | input | Quadrature clock input B with a filter circuit identical to input A. |
| 6 | MODE | input | 3-state input selecting resolution: logic 0 = x1, float = x2, logic 1 = x4. |
| 7 | DNCK | output | DOWN Clock output on the LS7083N, consisting of low-going pulses generated when the A input lags the B input. |
| 8 | UPCK | output | UP Clock output on the LS7083N, consisting of low-going pulses generated when the A input leads the B input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LSI/CSI |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
LS7083N-S - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ls7083n-s-etched.step/ls7083n-s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ls7083n-s.step/ls7083n-s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LSI/CSI datasheet (4 pp, sha256
af9dee3ffdab5f65, retrieved 2026-10-31, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LS7083N-S
**LSI/CSI** · Interface - Specialized · SOIC-8
LS7083N-S from LSI/CSI, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RBIAS | passive | External resistor connected between this pin and VSS sets the output clock pulse width TOW, which must be less than or equal to the A, B pulse separation (TOW ≤ TPS); RB range 2K to 10M ohm. |
| 2 | VDD | power_in | Positive supply terminal, +3V to +12V operation (VDD - VSS), absolute maximum 16V. |
| 3 | VSS | power_in | Negative supply terminal (ground). |
| 4 | A | input | Quadrature clock input A with a filter circuit to validate input logic level and eliminate encoder dither; logic 0 max 0.25VDD, logic 1 min 0.7VDD. |
| 5 | B | input | Quadrature clock input B with a filter circuit identical to input A. |
| 6 | MODE | input | 3-state input selecting resolution: logic 0 = x1, float = x2, logic 1 = x4. |
| 7 | DNCK | output | DOWN Clock output on the LS7083N, consisting of low-going pulses generated when the A input lags the B input. |
| 8 | UPCK | output | UP Clock output on the LS7083N, consisting of low-going pulses generated when the A input leads the B input. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LSI/CSI |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `LS7083N-S`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ls7083n-s-etched.step` / `ls7083n-s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ls7083n-s.step` / `ls7083n-s.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [LSI/CSI datasheet](docs/ls7083n-s-datasheet.pdf) (4 pp, sha256 `af9dee3ffdab5f65`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ls7083n-s-datasheet.pdf)