component

LR8341A-T50

Public Made by Adom

by adom

LR Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3L. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs lr8341a-t50: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
lr8341a-t50-etched.fit.json lr8341a-t50: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
lr8341a-t50-etched.glb lr8341a-t50: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
lr8341a-t50-etched.step lr8341a-t50: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
lr8341a-t50.glb Publish 0.1.0 · Ray
lr8341a-t50.kicad_mod Publish 0.1.0 · Ray
lr8341a-t50.kicad_sym Publish 0.1.0 · Ray
lr8341a-t50.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
lr8341a-t50.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json lr8341a-t50: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md lr8341a-t50: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

LR8341A-T50

LR · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L

LR8341A-T50 from LR, in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground / VSS return. All voltages are referenced to this pin. Labeled VSS on the SOT23-3L pin assignment diagram and GND on the block diagram.
2 VOUT power_out Regulated 5.0 V output (T50 variant). Nominal accuracy ±2% (VOUT0.99 to VOUT1.01) at IOUT=10 mA. Deliver up to 100 mA (160 mA absolute max). Requires a small output capacitor (~1 µF) for stability.
3 VIN power_in Unregulated input supply. Recommended operating range VOUT+2 V to 40 V; absolute maximum 55 V. Bypass with ~1 µF ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer LR
Package SOT-23-3L
Category PMIC
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • LR8341A-T50
  • LR8341A-T50M50

CAD (KiCad official)

  • Symbol: LR8341A-T50
  • Footprint: Package_TO_SOT_SMD:SOT-23-3
  • 3D model: SOT-23-3L (KiCad packages3D, STEP)
  • 3D model files: lr8341a-t50-etched.step / lr8341a-t50-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lr8341a-t50.step / lr8341a-t50.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
lr8341a-t50.step 59 KB You want the bare part, or you mark your own boards.
lr8341a-t50-etched.step 1.8 MB You want the part with LR8341A-T50 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 456 faces against 69 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LR datasheet (13 pp, sha256 0ef57f5e903211ad, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF