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LR8341A-T27

LR · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L

LR8341A-T27 from LR, in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference for the regulator; all voltages are specified relative to GND.
2 VOUT power_out Regulated 2.7V output (±1% at VIN=VOUT+2V, IOUT=10mA) delivering 100mA, needs at least 1uF ceramic output capacitor, short-circuit current limited to 15mA.
3 VIN power_in Input supply up to 40V operating (55V absolute maximum), needs at least 1uF ceramic bypass capacitor close to the pin.

Key specifications

Parameter Value
Manufacturer LR
Package SOT-23-3L
Category Power Management (PMIC)
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output current (IOUT) absolute maximum IOUT 160 mA 4
Line regulation ΔVOUT -30 30 mV VOUT+2V≤VIN≤40V, IOUT=5mA 4
Load regulation ΔVOUT -50 50 mV VIN=VOUT+2V, 1mA≤IOUT≤100mA 4
Dropout voltage at 50 mA VDrop 320 390 450 mV IOUT=50mA, ΔVOUT=±2%*VOUT 4
Dropout voltage at 100 mA VDrop 600 750 900 mV IOUT=100mA, ΔVOUT=±2%*VOUT 4
Quiescent current ISS 2 5 uA VIN=VOUT+2V 5
Temperature coefficient ΔVOUT/(ΔTa*VOUT) -100 50 100 ppm/℃ VIN=VOUT+1V, IOUT=10mA, -40℃≤Ta≤85℃; typ printed as ±50, max as ±100 5
Output voltage tolerance VOUT -2 2 % Printed ±2% of VOUT (high output accuracy) 4
Input voltage (electrical) VIN 40 V ISS=5uA 4
Maximum input supply voltage VIN 55 V 4
Power dissipation PD 250 mW SOT23-3L package 4
ESD HBM HBM -3000 3000 V POS/NEG; printed ±3000 4
Operating temperature TOPR -40 105 ℃ 4
Storage temperature TSTG -40 125 ℃ 4
Maximum junction temperature TJ(MAX) 150 °C Under absolute limiting operating conditions 8
Recommended maximum junction temperature TJ 125 °C Recommended for normal operation 8
Junction-to-ambient thermal resistance θJA 500 °C/W SOT23-3L 8
Input capacitor CIN CIN 1 uF Ceramic, recommended at least 1uF 8
Output capacitor COUT COUT 1 uF Ceramic, at least 1uF 8
Input and output capacitance (layout) CIN=COUT 1 10 uF Place as close to LDO as possible; check input capacitor voltage rating 10

CAD (KiCad official)

  • Symbol: LR8341A-T27
  • Footprint: Package_TO_SOT_SMD:SOT-23-3
  • 3D model: SOT-23-3L (KiCad packages3D, STEP)
  • 3D model files: lr8341a-t27-etched.step / lr8341a-t27-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lr8341a-t27.step / lr8341a-t27.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LR datasheet (12 pp, sha256 9debd2ff576f27c4, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF