component

LR8321A-T36

Public Made by Adom

by adom

LR Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LR8321A-T36

LR · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L

LR8321A-T36 from LR, in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference pin; all datasheet voltage values are specified relative to GND.
2 VOUT power_out Regulated fixed 3.6 V output for the LR8321A-T36, which requires a ceramic output capacitor of at least 1 µF and is current-limited to 120 mA typical (OCP), with a 20 mA typical short-circuit limit below 0.7 V.
3 VIN power_in Input supply pin rated 24 V maximum (32 V absolute maximum), which requires a ceramic bypass capacitor of at least 1 µF.

Key specifications

Parameter Value
Manufacturer LR
Package SOT-23-3L
Category Power Management (PMIC)
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Maximum input supply voltage VIN 32 V 4
Maximum output current IOUT 150 mA 4
Power dissipation (SOT23-3L) PD 250 mW SOT23-3L package 4
Operating temperature TOPR -40 105 ℃ 4
Storage temperature TSTG -40 125 ℃ 4
ESD human body model (H.B.M) -3000 3000 V H.B.M POS/NEG 4
Input voltage VIN 24 V ISS=5uA 4
Line regulation ΔVOUT -30 30 mV VOUT+2V≤VIN≤24V, IOUT=5mA 4
Load regulation ΔVOUT -50 50 mV VIN= VOUT+2V, 1mA≤IOUT≤100mA 4
Minimum dropout voltage VDrop 320 390 450 mV IOUT=50mA, ΔVOUT=±2%*VOUT 4
Minimum dropout voltage VDrop 600 750 900 mV IOUT=100mA, ΔVOUT=±2%*VOUT 4
Quiescent current ISS 1.5 5 uA VIN= VOUT+2V 5
Output temperature coefficient ΔVOUT/(ΔTa*VOUT) -100 50 100 ppm/℃ VIN= VOUT+2V, IOUT=10mA, -40℃≤Ta≤85℃ 5
Maximum junction temperature (absolute) TJ(MAX) 150 °C 8
Recommended maximum junction temperature TJ 125 °C normal operation 8
Input capacitor (recommended minimum) CIN 1 μF ceramic, recommended at least 8
Output capacitor (recommended minimum) COUT 1 μF ceramic, recommended at least 8
CIN and COUT layout range CIN=COUT 1 10 μF layout guidance, placed close to LDO 10
Junction-to-ambient thermal resistance (SOT23-3L) θJA 500 °C/W SOT23-3L 8

CAD (KiCad official)

  • Symbol: LR8321A-T36
  • Footprint: Package_TO_SOT_SMD:SOT-23-3
  • 3D model: SOT-23-3L (KiCad packages3D, STEP)
  • 3D model files: lr8321a-t36-etched.step / lr8321a-t36-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lr8321a-t36.step / lr8321a-t36.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LR datasheet (12 pp, sha256 75e1ff006d959d36, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF