LR7130-T

LR · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3

LR7130-T from LR, in a SOT-23-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VSS	power_in	Ground reference pin labelled VSS in the pin configuration; the absolute-maximum output voltage range is referenced to it (GND-0.3 V to VIN+0.3 V).
2	VOUT	power_out	Regulated output of the LR7130 (3.0 V nominal, 50 mA maximum output current), to be used with a 10 uF output capacitor as in the test conditions.
3	VIN	power_in	Input supply, rated up to 30 V in the features list with a 32 V absolute maximum; the LR7130 line regulation is specified for 4.0 V ≤ VIN ≤ 24 V.

Key specifications

Parameter	Value
Manufacturer	LR
Package	SOT-23-3
Category	Power Management (PMIC)
Pins	3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage	VIN			24	V	,	5
Output voltage	VOUT	2.94	3	3.06	V	VIN=5.0V,IOUT=10mA	5
Output current	IOUT	50			mA	VIN=5.0V	5
Line regulation			0.05	0.2	%/V	4.0V≤VIN≤24V, IOUT=10mA	5
Load regulation	△VOUT		30	50	mV	VIN=5.0V, 1mA≤IOUT≤60mA	5
Minimum dropout voltage	Vd	300	320	350	mV	IOUT=50fmA, △VOUT·2%	5
Quiescent current	ISS		1.8	6	uA	IOUT=0	5
Temperature coefficient		-100		100	ppm/℃	VIN=5.0V, IOUT=10mA, -40℃≤Ta≤+85℃	5
Input voltage (absolute maximum)	VIN			32	V		4
Power dissipation	PD			250	mW	SOT23-3 package	4
Operating temperature	TOPR	-40		85	℃		4
Storage temperature	TSTG	-40		125	℃		4
ESD rating (HBM)	ESD(HBM)			2	KV		4

CAD (KiCad official)

Symbol: LR7130-T
Footprint: Package_TO_SOT_SMD:SOT-23-3
3D model: SOT-23-3 (KiCad packages3D, STEP)
3D model files: lr7130-t-etched.step / lr7130-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lr7130-t.step / lr7130-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: LR datasheet (11 pp, sha256 dba609f0a891725c, retrieved 2026-10-21, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# LR7130-T

**LR** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3

LR7130-T from LR, in a SOT-23-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSS | power_in | Ground reference pin labelled VSS in the pin configuration; the absolute-maximum output voltage range is referenced to it (GND-0.3 V to VIN+0.3 V). |
| 2 | VOUT | power_out | Regulated output of the LR7130 (3.0 V nominal, 50 mA maximum output current), to be used with a 10 uF output capacitor as in the test conditions. |
| 3 | VIN | power_in | Input supply, rated up to 30 V in the features list with a 32 V absolute maximum; the LR7130 line regulation is specified for 4.0 V ≤ VIN ≤ 24 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | LR |
| Package | SOT-23-3 |
| Category | Power Management (PMIC) |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN |  |  | 24 | V |, | 5 |
| Output voltage | VOUT | 2.94 | 3 | 3.06 | V | VIN=5.0V,IOUT=10mA | 5 |
| Output current | IOUT | 50 |  |  | mA | VIN=5.0V | 5 |
| Line regulation |  |  | 0.05 | 0.2 | %/V | 4.0V≤VIN≤24V, IOUT=10mA | 5 |
| Load regulation | △VOUT |  | 30 | 50 | mV | VIN=5.0V, 1mA≤IOUT≤60mA | 5 |
| Minimum dropout voltage | Vd | 300 | 320 | 350 | mV | IOUT=50fmA, △VOUT·2% | 5 |
| Quiescent current | ISS |  | 1.8 | 6 | uA | IOUT=0 | 5 |
| Temperature coefficient |  | -100 |  | 100 | ppm/℃ | VIN=5.0V, IOUT=10mA, -40℃≤Ta≤+85℃ | 5 |
| Input voltage (absolute maximum) | VIN |  |  | 32 | V |  | 4 |
| Power dissipation | PD |  |  | 250 | mW | SOT23-3 package | 4 |
| Operating temperature | TOPR | -40 |  | 85 | ℃ |  | 4 |
| Storage temperature | TSTG | -40 |  | 125 | ℃ |  | 4 |
| ESD rating (HBM) | ESD(HBM) |  |  | 2 | KV |  | 4 |

## CAD (KiCad official)

- Symbol: `LR7130-T`
- Footprint: `Package_TO_SOT_SMD:SOT-23-3`
- 3D model: SOT-23-3 (KiCad packages3D, STEP)
- 3D model files: `lr7130-t-etched.step` / `lr7130-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lr7130-t.step` / `lr7130-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [LR datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588918087161171968) (11 pp, sha256 `dba609f0a891725c`, retrieved 2026-10-21, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lr7130-t-datasheet.pdf)