component
LR4056M-E
Public Made by Adomby adom
LR Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, ESOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 17d ago |
| viewers | 17d ago |
| lr4056m-e-etched.glb | 17d ago |
| lr4056m-e-etched.step | 17d ago |
| lr4056m-e-hero.glb | 17d ago |
| lr4056m-e-hero.overlay.json | 17d ago |
| lr4056m-e.glb | 17d ago |
| lr4056m-e.kicad_mod | 17d ago |
| lr4056m-e.kicad_sym | 17d ago |
| lr4056m-e.lbr | 17d ago |
| lr4056m-e.step | 17d ago |
| package.json | 17d ago |
| page.json | 17d ago |
| README.md | 17d ago |
LR4056M-E
LR · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · ESOP-8
LR4056M-E from LR, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TS | passive | External battery temperature sense input that uses an NTC divider; tying it to GND disables temperature monitoring, and charging pauses when VTS falls outside the OTPL/OTPH window. |
| 2 | PROG | passive | Charge current program pin where a 1% resistor to GND sets the constant charge current up to 1.0 A (RPROG = 0.91K gives about 1000 mA), with absolute maximum input of -0.3 to 6 V. |
| 3 | GND | power_in | Chip ground. |
| 4 | VDD | power_in | Input supply pin with a 4.5 to 6.0 V operating range, a 16 V absolute maximum, and 6.9 V (typical) overvoltage protection. |
| 5 | BAT | power_out | Battery connection and charge output that must connect to the battery positive terminal; absolute maximum range is -5 to 10 V. |
| 6 | STDBY | output | Open-drain charge-complete indicator output with an absolute maximum of 14 V and a low-level output of at most 2 V at 5 mA; tie to GND if unused. |
| 7 | CHRG | output | Open-drain charging indicator output that is pulled low during charging, with an absolute maximum of 14 V and a low-level output of at most 2 V at 5 mA; tie to GND if unused. |
| 8 | CE | input | Charge enable input where a high level of 1.5 to 6.0 V enables normal operation and a level at or below 0.2 V selects shutdown, with an absolute maximum of 14 V; leave floating if unused. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LR |
| Package | ESOP-8 |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD input voltage (absolute maximum) | VDD | -0.3 | 16 | V | 5 | ||
| CHRG pin input voltage | VCHRG | -0.3 | 14 | V | 5 | ||
| STDBY pin input voltage | VSTDBY | -0.3 | 14 | V | 5 | ||
| TS pin input voltage | VTS | -0.3 | 14 | V | 5 | ||
| BAT pin input voltage | VBAT | -5 | 10 | V | 5 | ||
| PROG pin input voltage | VPROG | -0.3 | 6 | V | 5 | ||
| CE pin input voltage | VCE | -0.3 | 14 | V | 5 | ||
| Operating temperature | TOAT | -40 | 85 | ℃ | 5 | ||
| Maximum junction temperature | TMJT | 150 | ℃ | 5 | |||
| Storage temperature | TST | -55 | 150 | ℃ | 5 | ||
| Package thermal resistance | RthJA | 58 | ℃/W | 5 | |||
| ESD human body model (HBM) | -2 | 2 | KV | 5 | |||
| VDD maximum input voltage | VDD_MAX | 16 | V | 6 | |||
| VDD operating voltage | VDD | 4.5 | 5 | 6 | V | 6 | |
| Input supply current, charging mode | IVDD-IBAT | 240 | 360 | uA | Charging mode, RPROG=1K | 6 | |
| Input supply current, standby mode (charge terminated) | IVDD-IBAT | 75 | 180 | uA | Standby mode (charge terminated) | 6 | |
| Input supply current, shutdown mode | IVDD-IBAT | 75 | 180 | uA | Shutdown mode: RPROG not connected, VDD<VBAT, VDD<VUVLO; CE=GND, OVP (condition text truncated in source) | 6 | |
| VDD undervoltage lockout threshold | VUV | 3.5 | V | VDD low to high | 6 | ||
| VDD undervoltage lockout hysteresis | VUV-HYS | 200 | mV | VDD high to low | 6 | ||
| VDD overvoltage protection threshold | VOVP | 6.3 | 6.9 | 7.5 | V | VDD low to high | 6 |
| VDD overvoltage protection hysteresis | VOVP-HYS | 500 | mV | VDD high to low | 6 | ||
| VDD-VBAT detection voltage (ASD), rising | VASD | 200 | mV | VDD low to high | 6 | ||
| VDD-VBAT detection voltage (ASD), falling | VASD | 50 | mV | VDD high to low | 6 | ||
| PROG voltage in constant-current mode | VPROG2 | 0.85 | 1 | 1.15 | V | VDD=5V, RPROG=0.91K | 6 |
| BAT charge current | IBAT | 900 | 1000 | 1050 | mA | VDD=5V, VBAT=3.9V, RPROG=0.91K | 6 |
| BAT leakage with VDD floating | 0.5 | 3 | uA | VDD floating, VBAT=4.0V | 6 | ||
| Trickle charge current | ITRIKL | 77 | 100 | 120 | mA | VBAT<VTRIKL, RPROG=0.91K | 6 |
| 1C/10 charge termination current | ITERM | 100 | mA | RPROG=0.91K | 6 | ||
| Trickle charge detection voltage | VTRKL | 2.6 | 2.8 | 3 | V | VBAT low to high | 6 |
| Trickle charge detection recovery hysteresis | VTRHYS | 150 | mV | VBAT high to low | 6 | ||
| PROG pin pull-up current | IPROG | 1 | uA | 6 | |||
| Float (full charge) detection voltage, LR4056M-E | VFLOAT | 4.15 | 4.2 | 4.25 | V | VDD=5V, RPROG=0.91K | 6 |
| Recharge battery voltage threshold | VRECHARG | 150 | mV | VFLOAT-VRECHARG | 6 | ||
| Full charge detection delay | TDELAY | 0.8 | 1.8 | 4 | ms | IBAT falls below 0.1 ICHRG | 6 |
| Recharge detection delay | TRECHARGE | 0.8 | 1.8 | 4 | ms | 7 | |
| Power MOSFET on-resistance | RDS_ON | 700 | mΩ | VBAT=3.8V, ICHRG=1A, RPROG=1K | 7 | ||
| CE high-level input voltage (normal operation) | VCEH | 1.5 | 6 | V | Normal operation | 7 | |
| CE low-level input voltage (shutdown mode) | VCEL | 0.2 | V | Shutdown mode | 7 | ||
| Built-in temperature compensation (thermal regulation) threshold | OTC | 130 | ℃ | VDD=5V, VBAT=3.0V, RPROG=0.91K | 7 | ||
| External over-temperature detection threshold (high) | OTPH | 43 | 45 | %×VDD | TS connected to NTC resistor | 7 | |
| External under-temperature detection threshold (low) | OTPL | 80 | 82 | %×VDD | TS connected to NTC resistor | 7 | |
| CHRG pin output low voltage | VCHRGL | 1 | 2 | V | ICHRG=5mA | 7 | |
| STDBY pin output low voltage | VSTDBYL | 1 | 2 | V | ISTDBY=5mA | 7 |
CAD (KiCad official)
- Symbol:
LR4056M-E - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files:
lr4056m-e-etched.step/lr4056m-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lr4056m-e.step/lr4056m-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LR datasheet (11 pp, sha256
07e2bf3d47a2c37f, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).