component
LPW5202FDB5F21
Public Made by Adomby adom
LOWPOWER Power Distribution Switches, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLPW5202FDB5F21
LOWPOWER · Power Distribution Switches · SOT-23-5
LPW5202FDB5F21 from LOWPOWER, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Output of power switch. |
| 2 | GND | power_in | Ground. |
| 3 | FLAGB | output | Open-drain active-low flag pin to indicate fault condition. |
| 4 | EN | input | Active-high device enable pin. |
| 5 | IN | power_in | Power supply and input of power switch, 2.4V to 6V operating range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LOWPOWER |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Current limit level (LPW5202xxx21, fixed 2.3A variant) | ILIM | 2.1 | 2.3 | 2.5 | A | VIN = 5V, VOUT = 4.5V, TA=25°C | 6 |
| Under voltage lockout level (IN falling) | VUVLO_F | 2.25 | 2.5 | 2.75 | V | IN voltage falling | 5 |
| Under voltage lockout level (IN rising) | VUVLO_R | 2.4 | 2.65 | 2.9 | V | IN voltage rising | 5 |
| Enable pull-down resistor | RPD | 1 | 1.4 | 1.8 | MΩ | VIN = 5V, TA=25°C | 6 |
| Output auto discharge | RDIS | 90 | 110 | 130 | Ω | VIN = 5V, EN flip from high to low | 6 |
| OCP response time | tOCP | 3 | 7 | 15 | μs | VIN = 5V, TA = 25°C, time from IOUT hits IOCP to IOUT stop rising | 6 |
| Input voltage (recommended operating) | 2.4 | 6 | V | 5 | |||
| Enable voltage (recommended operating) | 0 | 6 | V | 5 | |||
| Ambient temperature (recommended operating) | TA | -40 | 85 | °C | 5 | ||
| IN to GND | -0.3 | 7 | V | 5 | |||
| OUT to GND | -0.3 | 7 | V | 5 | |||
| EN to GND | -0.3 | 7 | V | 5 | |||
| ISET to GND | -0.3 | 7 | V | 5 | |||
| FLAGB to GND | -0.3 | 7 | V | 5 | |||
| Maximum junction temperature | 150 | °C | 5 | ||||
| Storage temperature range | -65 | 150 | °C | 5 | |||
| Maximum soldering temperature (at leads) | 260 | °C | at leads, 10 seconds | 5 | |||
| ESD HBM (Human Body Model) | -4000 | 4000 | V | JEDEC JS-001 | 5 | ||
| ESD CDM (Charged Device Model) | -500 | 500 | V | JEDEC JS-002 | 5 | ||
| Maximum power dissipation (PD) | PD | 0.6 | W | TA <= 25℃ | 5 | ||
| Thermal resistance, junction to ambient | θJA | 203 | °C/W | Note 2: 2S2P JEDEC standard PCB | 5 | ||
| Thermal resistance, junction to case | θJC | 120 | °C/W | Note 2: 2S2P JEDEC standard PCB | 5 |
CAD (KiCad official)
- Symbol:
LPW5202FDB5F21 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
lpw5202fdb5f21-etched.step/lpw5202fdb5f21-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lpw5202fdb5f21.step/lpw5202fdb5f21.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LOWPOWER datasheet (14 pp, sha256
a2d63b77e87fdc1c, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).