LPV324MT from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUT A	output	Output of channel A, which swings rail-to-rail (V+ − 3.5 mV to V− + 90 mV at a 100 kΩ load).
2	IN A-	input	Inverting input of channel A, with input common-mode range of −0.2 V to V+ − 0.8 V.
3	IN A+	input	Noninverting input of channel A, with input common-mode range of −0.2 V to V+ − 0.8 V.
4	V+	power_in	Positive (highest) power supply; recommended supply range is 2.7 V to 5 V, with an absolute maximum of 5.5 V.
5	IN B+	input	Noninverting input of channel B, with input common-mode range of −0.2 V to V+ − 0.8 V.
6	IN B-	input	Inverting input of channel B, with input common-mode range of −0.2 V to V+ − 0.8 V.
7	OUT B	output	Output of channel B, which swings rail-to-rail (V+ − 3.5 mV to V− + 90 mV at a 100 kΩ load).
8	OUT C	output	Output of channel C, which swings rail-to-rail (V+ − 3.5 mV to V− + 90 mV at a 100 kΩ load).
9	IN C-	input	Inverting input of channel C, with input common-mode range of −0.2 V to V+ − 0.8 V.
10	IN C+	input	Noninverting input of channel C, with input common-mode range of −0.2 V to V+ − 0.8 V.
11	V-	power_in	Negative (lowest) power supply, which is the GND reference for the device.
12	IN D+	input	Noninverting input of channel D, with input common-mode range of −0.2 V to V+ − 0.8 V.
13	IN D-	input	Inverting input of channel D, with input common-mode range of −0.2 V to V+ − 0.8 V.
14	OUT D	output	Output of channel D, which swings rail-to-rail (V+ − 3.5 mV to V− + 90 mV at a 100 kΩ load).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-14
Category	Amplifiers
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage (V+, V−), absolute maximum	V+, V−			5.5	V		4
Junction temperature, TJ(MAX)	TJ(MAX)			150	°C		4
Storage temperature	Tstg	-65		150	°C		4
Electrostatic discharge, human-body model (LPV324-N in D and PW packages)	V(ESD)	-2000		2000	V	Human-body model, ANSI/ESDA/JEDEC JS-001	4
Electrostatic discharge, machine model (LPV324-N in D and PW packages)	V(ESD)	-100		100	V	Machine model	4
Supply voltage, recommended operating		2.7		5	V		4
Operating temperature		-40		85	°C		4
Input offset voltage, 2.7 V	VOS		1.2	7	mV		5
Input bias current, 2.7 V	IB		1.7	50	nA		5
Input offset current, 2.7 V	IOS		0.6	40	nA		5
Common mode rejection ratio, 2.7 V	CMRR	50	70		dB	0 V ≤ VCM ≤ 1.7 V	5
Power supply rejection ratio, 2.7 V	PSRR	50	65		dB	2.7 V ≤ V+ ≤ 5 V, VO = 1 V, VCM = 1 V	5
Input common-mode voltage, lower limit, 2.7 V	VCM	-0.2	0		V	For CMRR ≥ 50 dB	5
Input common-mode voltage, upper limit, 2.7 V	VCM	1.7	1.9		V	For CMRR ≥ 50 dB	5
Output swing, second limit at 2.7 V (sourcing/sinking label not printed)	VO		80	180	mV	RL = 100 kΩ to 1.35 V	5
Supply current, LPV324-N all four amplifiers, 2.7 V	IS		16	24	µA	LPV324-N, all four amplifiers	5
Input offset voltage, TJ = 25°C, 5 V	VOS		1.5	7	mV	TJ = 25°C	5
Input offset voltage, 5 V	VOS			10	mV	TJ = -40°C to 85°C	5
Input bias current, 5 V	IB		2	50	nA	TJ = 25°C	5
Input bias current, 5 V	IB			60	nA	TJ = -40°C to 85°C	5
Input offset current, 5 V	IOS		0.6	40	nA	TJ = 25°C	5
Input offset current, 5 V	IOS			50	nA	TJ = -40°C to 85°C	5
Common mode rejection ratio, 5 V	CMRR	50	71		dB	0 V ≤ VCM ≤ 4 V	5
Power supply rejection ratio, 5 V	PSRR	50	65		dB	2.7 V ≤ V+ ≤ 5 V, VO = 1 V, VCM = 1 V	5
Input common-mode voltage, lower limit, 5 V	VCM	-0.2	0		V	For CMRR ≥ 50 dB	6
Input common-mode voltage, upper limit, 5 V	VCM	4	4.2		V	For CMRR ≥ 50 dB	6
Large signal voltage gain, TJ = 25°C, 5 V	AV	15	100		V/mV	RL = 100 kΩ, TJ = 25°C	6
Large signal voltage gain, 5 V	AV	10			V/mV	RL = 100 kΩ, TJ = -40°C to 85°C	6
Output swing, sinking, 5 V	VO		90	180	mV	RL = 100 kΩ to 2.5 V, TJ = 25°C	6
Output swing, sinking, 5 V	VO			220	mV	RL = 100 kΩ to 2.5 V, TJ = -40°C to 85°C	6
Output short circuit current, sourcing, 5 V	IO	2	16		mA	LPV3xx-N, VO = 0 V	6
Output short circuit current, sinking, 5 V	IO	11	16		mA	LPV324-N and LPV358-N, VO = 5 V	6
Supply current, LPV324-N all four amplifiers, TJ = 25°C, 5 V	IS		28	42	µA	LPV324-N, all four amplifiers, TJ = 25°C	6
Supply current, LPV324-N all four amplifiers, 5 V	IS			46	µA	LPV324-N, all four amplifiers, TJ = -40°C to 85°C	6
Thermal resistance, junction-to-ambient	RθJA		132.7		°C/W	PW (TSSOP) 14 PINS package	4
Thermal resistance, junction-to-case (top)	RθJC(top)		59.1		°C/W	PW (TSSOP) 14 PINS package	4
Thermal resistance, junction-to-board	RθJB		75.1		°C/W	PW (TSSOP) 14 PINS package	4
Junction-to-top characterization parameter	ψJT		10.8		°C/W	PW (TSSOP) 14 PINS package	4
Junction-to-board characterization parameter	ψJB		74.58		°C/W	PW (TSSOP) 14 PINS package	4

CAD (KiCad official)

Symbol: LPV324MT
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: lpv324mt-etched.step / lpv324mt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lpv324mt.step / lpv324mt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (42 pp, sha256 f1b562f7c5f07b4e, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LPV324MT

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