# LPC11U35FBD48

**NXP Semicon** · NXP MCU · LQFP-48(7x7)

LPC11U35FBD48 from NXP Semicon, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PIO1_25/CT32B0_MAT1 | bidirectional | General purpose digital input/output pin with 32-bit timer 0 match output 1 function (5 V tolerant pad with configurable pull-up/pull-down). |
| 2 | PIO1_19/DTR/SSEL1 | bidirectional | General purpose digital input/output pin with USART DTR output and SSP1 slave select function (5 V tolerant pad with configurable pull-up/pull-down). |
| 3 | RESET/PIO0_0 | input | External reset input with 20 ns glitch filter; a LOW-going pulse as short as 50 ns resets the device, and the pin is 5 V tolerant and requires an external pull-up for Deep power-down mode. |
| 4 | PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE | bidirectional | General purpose digital input/output pin; a LOW level during reset starts the ISP command handler or USB device enumeration, and it also provides CLKOUT, CT32B0_MAT2 and USB_FTOGGLE functions. |
| 5 | VSS | power_in | Ground. |
| 6 | XTALIN | input | Input to the oscillator circuit and internal clock generator circuits; input voltage must not exceed 1.8 V. |
| 7 | XTALOUT | output | Output from the oscillator amplifier. |
| 8 | VDD | power_in | Supply voltage to the internal regulator, the external rail, and the ADC; also used as the ADC reference voltage. |
| 9 | PIO0_20/CT16B1_CAP0 | bidirectional | General purpose digital input/output pin with 16-bit timer 1 capture input 0 function. |
| 10 | PIO0_2/SSEL0/CT16B0_CAP0/IOH_0 | bidirectional | General purpose digital input/output pin with SSP0 slave select, 16-bit timer 0 capture input 0 and I/O Handler functions (IOH_0 on LPC11U37HFBD64/401 only). |
| 11 | PIO1_26/CT32B0_MAT2/RXD/IOH_19 | bidirectional | General purpose digital input/output pin with 32-bit timer 0 match output 2, USART RXD and I/O Handler functions (IOH_19 on LPC11U37HFBD64/401 only). |
| 12 | PIO1_27/CT32B0_MAT3/TXD/IOH_20 | bidirectional | General purpose digital input/output pin with 32-bit timer 0 match output 3, USART TXD and I/O Handler functions (IOH_20 on LPC11U37HFBD64/401 only). |
| 13 | PIO1_20/DSR/SCK1 | bidirectional | General purpose digital input/output pin with USART DSR input and SSP1 serial clock function. |
| 14 | PIO0_3/USB_VBUS/IOH_1 | bidirectional | General purpose digital input/output pin; a LOW level during reset starts the ISP handler and a HIGH level starts USB enumeration, and the pin monitors USB bus power as USB_VBUS. |
| 15 | PIO0_4/SCL/IOH_2 | bidirectional | Open-drain general purpose digital input/output pin with I2C-bus SCL function; high-current sink only if I2C Fast-mode Plus is selected. |
| 16 | PIO0_5/SDA/IOH_3 | bidirectional | Open-drain general purpose digital input/output pin with I2C-bus SDA function; high-current sink only if I2C Fast-mode Plus is selected. |
| 17 | PIO0_21/CT16B1_MAT0/MOSI1 | bidirectional | General purpose digital input/output pin with 16-bit timer 1 match output 0 and SSP1 MOSI functions. |
| 18 | PIO1_23/CT16B1_MAT1/SSEL1 | bidirectional | General purpose digital input/output pin with 16-bit timer 1 match output 1 and SSP1 slave select functions. |
| 19 | USB_DM | bidirectional | USB bidirectional D- line; pad is designed to USB specification revision 2.0 (Full-speed and Low-speed mode only) and is not 5 V tolerant. |
| 20 | USB_DP | bidirectional | USB bidirectional D+ line; pad is designed to USB specification revision 2.0 (Full-speed and Low-speed mode only) and is not 5 V tolerant. |
| 21 | PIO1_24/CT32B0_MAT0 | bidirectional | General purpose digital input/output pin with 32-bit timer 0 match output 0 function. |
| 22 | PIO0_6/USB_CONNECT/SCK0/IOH_4 | bidirectional | General purpose digital input/output pin with USB_CONNECT output for switching an external 1.5 k resistor (SoftConnect) and SSP0 serial clock function. |
| 23 | PIO0_7/CTS/IOH_5 | bidirectional | General purpose digital input/output pin with high-current output driver and USART CTS input function. |
| 24 | PIO1_28/CT32B0_CAP0/SCLK | bidirectional | General purpose digital input/output pin with 32-bit timer 0 capture input 0 and USART synchronous serial clock functions. |
| 25 | PIO1_31 | bidirectional | General purpose digital input/output pin. |
| 26 | PIO1_21/DCD/MISO1 | bidirectional | General purpose digital input/output pin with USART DCD input and SSP1 MISO function. |
| 27 | PIO0_8/MISO0/CT16B0_MAT0/R/IOH_6 | bidirectional | General purpose digital input/output pin with SSP0 MISO and 16-bit timer 0 match output 0 functions (reserved function R also listed). |
| 28 | PIO0_9/MOSI0/CT16B0_MAT1/R/IOH_7 | bidirectional | General purpose digital input/output pin with SSP0 MOSI and 16-bit timer 0 match output 1 functions (reserved function R also listed). |
| 29 | SWCLK/PIO0_10/SCK0/CT16B0_MAT2 | input | Serial wire clock and test clock TCK for JTAG interface; also general purpose I/O PIO0_10 with SSP0 SCK0 and 16-bit timer 0 match output 2 functions. |
| 30 | PIO0_22/AD6/CT16B1_MAT1/MISO1 | bidirectional | General purpose digital input/output pin with ADC input 6, 16-bit timer 1 match output 1 and SSP1 MISO functions. |
| 31 | PIO1_29/SCK0/CT32B0_CAP1 | bidirectional | General purpose digital input/output pin with SSP0 serial clock and 32-bit timer 0 capture input 1 functions. |
| 32 | TDI/PIO0_11/AD0/CT32B0_MAT3 | input | Test Data In for JTAG interface; also general purpose I/O PIO0_11 with ADC input 0 and 32-bit timer 0 match output 3 functions. |
| 33 | TMS/PIO0_12/AD1/CT32B1_CAP0 | input | Test Mode Select for JTAG interface; also general purpose I/O PIO0_12 with ADC input 1 and 32-bit timer 1 capture input 0 functions. |
| 34 | TDO/PIO0_13/AD2/CT32B1_MAT0 | output | Test Data Out for JTAG interface; also general purpose I/O PIO0_13 with ADC input 2 and 32-bit timer 1 match output 0 functions. |
| 35 | TRST/PIO0_14/AD3/CT32B1_MAT1 | input | Test Reset for JTAG interface; also general purpose I/O PIO0_14 with ADC input 3 and 32-bit timer 1 match output 1 functions. |
| 36 | PIO1_13/DTR/CT16B0_MAT0/TXD | bidirectional | General purpose digital input/output pin with USART DTR and TXD outputs and 16-bit timer 0 match output 0 function. |
| 37 | PIO1_14/DSR/CT16B0_MAT1/RXD | bidirectional | General purpose digital input/output pin with USART DSR and RXD inputs and 16-bit timer 0 match output 1 function. |
| 38 | PIO1_22/RI/MOSI1 | bidirectional | General purpose digital input/output pin with USART RI input and SSP1 MOSI function. |
| 39 | SWDIO/PIO0_15/AD4/CT32B1_MAT2 | bidirectional | Serial wire debug input/output; also general purpose I/O PIO0_15 with ADC input 4 and 32-bit timer 1 match output 2 functions. |
| 40 | PIO0_16/AD5/CT32B1_MAT3/IOH_8/WAKEUP | bidirectional | General purpose digital input/output pin with ADC input 5 and 32-bit timer 1 match output 3 functions; WAKEUP input for Deep power-down exit with 20 ns glitch filter. |
| 41 | VSS | power_in | Ground. |
| 42 | PIO0_23/AD7/IOH_9 | bidirectional | General purpose digital input/output pin with ADC input 7 function (IOH_9 on LPC11U37HFBD64/401 only). |
| 43 | PIO1_15/DCD/CT16B0_MAT2/SCK1 | bidirectional | General purpose digital input/output pin with USART DCD input, 16-bit timer 0 match output 2 and SSP1 serial clock functions. |
| 44 | VDD | power_in | Supply voltage to the internal regulator, the external rail, and the ADC; also used as the ADC reference voltage. |
| 45 | PIO0_17/RTS/CT32B0_CAP0/SCLK | bidirectional | General purpose digital input/output pin with USART RTS output, 32-bit timer 0 capture input 0 and USART synchronous clock functions. |
| 46 | PIO0_18/RXD/CT32B0_MAT0 | bidirectional | General purpose digital input/output pin with USART RXD input (used in UART ISP mode) and 32-bit timer 0 match output 0 functions. |
| 47 | PIO0_19/TXD/CT32B0_MAT1 | bidirectional | General purpose digital input/output pin with USART TXD output (used in UART ISP mode) and 32-bit timer 0 match output 1 functions. |
| 48 | PIO1_16/RI/CT16B0_CAP0 | bidirectional | General purpose digital input/output pin with USART RI input and 16-bit timer 0 capture input 0 functions. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | NXP Semicon |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply voltage (core and external rail) | VDD | -0.5 |  | 4.6 | V |  | 31 |
| input voltage, 5 V tolerant digital I/O pins | VI | -0.5 |  | 5.5 | V | VDD ≥ 1.8 V | 31 |
| input voltage | VI | -0.5 |  | 3.6 | V | VDD = 0 V | 31 |
| input voltage, 5 V tolerant open-drain pins PIO0_4 and PIO0_5 | VI | -0.5 |  | 5.5 | V |  | 31 |
| analog input voltage | VIA | -0.5 |  | 4.6 | V | pin configured as analog input | 31 |
| supply current per supply pin | IDD |  |  | 100 | mA | per supply pin | 31 |
| ground current per ground pin | ISS |  |  | 100 | mA | per ground pin | 31 |
| I/O latch-up current | Ilatch |  |  | 100 | mA | (0.5VDD) < VI < (1.5VDD); Tj < 125 C | 31 |
| storage temperature non-operating | Tstg | -65 |  | 150 | C | non-operating | 31 |
| maximum junction temperature | Tj(max) |  |  | 150 | C |  | 31 |
| total power dissipation (per package) | Ptot(pack) |  |  | 1.5 | W | based on package heat transfer, not device power consumption | 31 |
| electrostatic discharge voltage | VESD |  |  | 6500 | V | human body model; all pins | 31 |
| supply voltage (core and external rail) | VDD | 1.8 | 3.3 | 3.6 | V |  | 32 |
| input voltage, pin configured to provide a digital function | VI | 0 |  | 5 | V | VDD 1.8 V | 32 |
| input voltage | VI | 0 |  | 3.6 | V | VDD = 0 V | 32 |
| output voltage | VO | 0 |  |  | V | output active; max printed as VDD | 32 |
| LOW-level output voltage | VOL |  |  | 0.4 | V | 2.0 V ≤ VDD ≤ 3.6 V; IOL = 4 mA | 32 |
| HIGH-level output current | IOH | 4 |  |  | mA | VOH = VDD - 0.4 V; 2.0 V ≤ VDD ≤ 3.6 V | 32 |
| HIGH-level output current | IOH | 3 |  |  | mA | 1.8 V ≤ VDD < 2.0 V | 32 |
| LOW-level output current | IOL | 4 |  |  | mA | VOL = 0.4 V; 2.0 V ≤ VDD ≤ 3.6 V | 33 |
| LOW-level output current | IOL | 3 |  |  | mA | VOL = 0.4 V; 1.8 V ≤ VDD < 2.0 V | 33 |
| HIGH-level short-circuit output current | IOHS |  |  | 45 | mA | VOH = 0 V | 33 |
| LOW-level short-circuit output current | IOLS |  |  | 50 | mA | VOL = VDD | 33 |
| pull-down current | Ipd | 10 | 50 | 150 | µA | VI = 5 V | 33 |
| pull-up current | Ipu | 15 | 50 | 85 | µA | VI = 0 V; 2.0 V ≤ VDD ≤ 3.6 V | 33 |
| pull-up current | Ipu | 10 | 50 | 85 | µA | VI = 0 V; 1.8 V ≤ VDD < 2.0 V | 34 |
| LOW-level input current | IIL |  | 0.5 | 10 | nA | VI = 0 V; on-chip pull-up resistor disabled | 32 |
| HIGH-level input current | IIH |  | 0.5 | 10 | nA | VI = VDD; on-chip pull-down resistor disabled | 32 |
| OFF-state output current | IOZ |  | 0.5 | 10 | nA | VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled | 32 |
| input leakage current | ILI |  |  | 24 | µA | VI = VDD | 34 |
| LOW-level output current, I2C-bus standard mode | IOL | 3.5 |  |  | mA | VOL = 0.4 V; 2.0 V ≤ VDD ≤ 3.6 V | 34 |
| LOW-level output current, I2C-bus standard mode | IOL | 3 |  |  | mA | VOL = 0.4 V; 1.8 V ≤ VDD < 2.0 V | 34 |
| LOW-level output current, I2C-bus Fast-mode Plus | IOL | 20 |  |  | mA | VOL = 0.4 V; 2.0 V ≤ VDD ≤ 3.6 V | 34 |
| LOW-level output current, I2C-bus Fast-mode Plus | IOL | 16 |  |  | mA | VOL = 0.4 V; 1.8 V ≤ VDD < 2.0 V | 34 |
| crystal input voltage | Vi(xtal) | 0.5 | 1.8 | 1.95 | V |  | 34 |
| crystal output voltage | Vo(xtal) | 0.5 | 1.8 | 1.95 | V |  | 34 |
| OFF-state output current, USB pins | IOZ |  |  | 10 | µA | 0 V < VI < 3.3 V | 34 |
| bus supply voltage | VBUS |  |  | 5.25 | V |  | 34 |
| differential input sensitivity voltage | VDI | 0.2 |  |  | V | (D+) - (D-) | 34 |
| differential common mode voltage range | VCM | 0.8 |  | 2.5 | V | includes VDI range | 34 |
| single-ended receiver switching threshold voltage | Vth(rs)se | 0.8 |  | 2 | V |  | 34 |
| LOW-level output voltage, USB | VOL |  |  | 0.18 | V | for low-/full-speed; RL of 1.5 kΩ to 3.6 V | 34 |
| HIGH-level output voltage, USB | VOH | 2.8 |  | 3.5 | V | driven; for low-/full-speed; RL of 15 kΩ to GND | 34 |
| transceiver capacitance | Ctrans |  |  | 20 | pF | pin to GND | 34 |
| pin capacitance, analog function | Cio |  |  | 7.1 | pF | pins configured for analog function | 35 |
| pin capacitance, I2C-bus pins | Cio |  |  | 2.5 | pF | PIO0_4 and PIO0_5 | 35 |
| pin capacitance, GPIO | Cio |  |  | 2.8 | pF | pins configured as GPIO | 35 |
| differential linearity error | ED |  |  | 1 | LSB |  | 36 |
| integral non-linearity | EL(adj) |  |  | 1.5 | LSB |  | 36 |
| offset error | EO |  |  | 3.5 | LSB |  | 36 |
| gain error | EG |  |  | 0.6 | % |  | 36 |
| absolute error | ET |  |  | 4 | LSB |  | 36 |
| active mode supply current, 12 MHz | IDD |  | 2 |  | mA | Active mode; VDD = 3.3 V; Tamb = 25 C; code while(1){} executed from flash; system clock = 12 MHz | 32 |
| active mode supply current, 50 MHz | IDD |  | 7 |  | mA | Active mode; VDD = 3.3 V; Tamb = 25 C; system clock = 50 MHz | 32 |
| sleep mode supply current | IDD |  | 1 |  | mA | Sleep mode; VDD = 3.3 V; Tamb = 25 C; system clock = 12 MHz | 32 |
| deep-sleep mode supply current | IDD |  | 300 |  | µA | Deep-sleep mode; VDD = 3.3 V; Tamb = 25 C | 32 |
| power-down mode supply current | IDD |  | 2 |  | µA | Power-down mode; VDD = 3.3 V; Tamb = 25 C | 32 |
| deep power-down mode supply current | IDD |  | 220 |  | nA | Deep power-down mode; VDD = 3.3 V; Tamb = 25 C | 32 |

## CAD (KiCad official)

- Symbol: `LPC11U35FBD48`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `lpc11u35fbd48-etched.step` / `lpc11u35fbd48-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lpc11u35fbd48.step` / `lpc11u35fbd48.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [NXP Semicon datasheet](https://www.nxp.com/docs/en/data-sheet/LPC11U35FBD48.pdf) (77 pp, sha256 `85cf6c6f424ce8d4`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lpc11u35fbd48-datasheet.pdf)