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LPC1114FHN33
Public Made by Adomby adom
NXP Semicon NXP MCU, QFN-32-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLPC1114FHN33
NXP Semicon · NXP MCU · QFN-32-EP(7x7)
LPC1114FHN33 from NXP Semicon, in a QFN-32-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PIO2_0/DTR | bidirectional | General-purpose 5 V-tolerant digital I/O with internal pull-up and configurable pull-up/pull-down and hysteresis; alternate function is UART DTR output. |
| 2 | RESET/PIO0_0 | input | Active-low external reset input (Schmitt trigger) that resets the device and forces execution from address 0; the PIO0_0 function has a 10 ns glitch filter, the pin is disabled in deep power-down, and an external pull-up is required in deep-sleep mode. |
| 3 | PIO0_1/CLKOUT/CT32B0_MAT2 | bidirectional | 5 V-tolerant general-purpose I/O that, when low at reset, starts the ISP command handler; alternate functions are CLKOUT clock output and CT32B0_MAT2 match output. |
| 4 | XTALIN | input | Input to the oscillator and internal clock generator circuits; the input voltage is limited to 1.8 V (section 11.2) and it may be left floating or grounded when the system oscillator is not used. |
| 5 | XTALOUT | output | Output of the oscillator amplifier that must be left unconnected when the system oscillator is not used. |
| 6 | VDD | power_in | 3.3 V input/output supply that also powers the internal regulator and ADC and serves as the ADC reference voltage. |
| 7 | PIO1_8/CT16B1_CAP0 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up; alternate function is CT16B1_CAP0 capture input 0 of 16-bit timer 1. |
| 8 | PIO0_2/SSEL0/CT16B0_CAP0 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up; alternate functions are SSP0 slave select (SSEL0) and CT16B0_CAP0 capture input 0 of 16-bit timer 0. |
| 9 | PIO0_3 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up and no alternate function listed in the HVQFN33 table. |
| 10 | PIO0_4/SCL | bidirectional | I2C clock line (SCL) that meets I2C standard-mode and Fast-mode Plus specifications and has high current sink capability only when Fast-mode Plus is selected in the I/O configuration register. |
| 11 | PIO0_5/SDA | bidirectional | Open-drain I2C data line (SDA) that meets I2C standard-mode and Fast-mode Plus specifications and has high current sink capability only when Fast-mode Plus is selected in the I/O configuration register. |
| 12 | PIO1_9/CT16B1_MAT0 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up; alternate function is CT16B1_MAT0 match output 0 of 16-bit timer 1. |
| 13 | PIO3_4 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up and no alternate function listed in the HVQFN33 table. |
| 14 | PIO3_5 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up and no alternate function listed in the HVQFN33 table. |
| 15 | PIO0_6/SCK0 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up; alternate function is SSP0 serial clock SCK0. |
| 16 | PIO0_7/CTS | bidirectional | 5 V-tolerant general-purpose I/O with pull-up and high-current output drive; alternate function is UART CTS input. |
| 17 | PIO0_8/MISO0/CT16B0_MAT0 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up; alternate functions are SSP0 MISO0 and CT16B0_MAT0 match output 0. |
| 18 | PIO0_9/MOSI0/CT16B0_MAT1 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up; alternate functions are SSP0 MOSI0 and CT16B0_MAT1 match output 1. |
| 19 | SWCLK/PIO0_10/SCK0/CT16B0_MAT2 | input | Serial Wire Debug clock input (SWCLK) with pull-up that is shared with GPIO PIO0_10, SSP0 serial clock SCK0 and CT16B0_MAT2 match output 2. |
| 20 | PIO1_10/AD6/CT16B1_MAT1 | bidirectional | 5 V-tolerant digital I/O with pull-up whose digital part is disabled when used as ADC input 6, and the ADC input is not 5 V-tolerant; alternate function is CT16B1_MAT1 match output 1. |
| 21 | R/PIO0_11/AD0/CT32B0_MAT3 | bidirectional | Reserved (R) function configured in IOCONFIG at reset; GPIO PIO0_11 with ADC input 0 and CT32B0_MAT3 match output 3, where the digital part is 5 V-tolerant only and the ADC input is not 5 V-tolerant. |
| 22 | R/PIO1_0/AD1/CT32B1_CAP0 | bidirectional | Reserved (R) function configured in IOCONFIG at reset; GPIO PIO1_0 with ADC input 1 and CT32B1_CAP0 capture input 0, where the ADC input is not 5 V-tolerant. |
| 23 | R/PIO1_1/AD2/CT32B1_MAT0 | bidirectional | Reserved (R) function configured in IOCONFIG at reset; GPIO PIO1_1 with ADC input 2 and CT32B1_MAT0 match output 0, where the ADC input is not 5 V-tolerant. |
| 24 | R/PIO1_2/AD3/CT32B1_MAT1 | bidirectional | Reserved (R) function configured in IOCONFIG at reset; GPIO PIO1_2 with ADC input 3 and CT32B1_MAT1 match output 1, where the ADC input is not 5 V-tolerant. |
| 25 | SWDIO/PIO1_3/AD4/CT32B1_MAT2 | bidirectional | Serial Wire Debug data input/output (SWDIO) with pull-up that is shared with GPIO PIO1_3, ADC input 4 and CT32B1_MAT2 match output 2. |
| 26 | PIO1_4/AD5/CT32B1_MAT3/WAKEUP | bidirectional | GPIO PIO1_4 with a 10 ns glitch filter that also serves as the WAKEUP input (20 ns glitch filter) for deep power-down/deep-sleep wake-up, where a 50 ns low pulse wakes the device and an external pull-up is needed in deep power-down. |
| 27 | PIO1_11/AD7 | bidirectional | 5 V-tolerant digital I/O with pull-up whose digital part is disabled when used as ADC input 7, and the ADC input is not 5 V-tolerant. |
| 28 | PIO3_2 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up and no alternate function listed in the HVQFN33 table. |
| 29 | VDD | power_in | 3.3 V input/output supply that also powers the internal regulator and ADC and serves as the ADC reference voltage. |
| 30 | PIO1_5/RTS/CT32B0_CAP0 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up; alternate functions are UART RTS output and CT32B0_CAP0 capture input 0. |
| 31 | PIO1_6/RXD/CT32B0_MAT0 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up; alternate functions are UART RXD receiver input and CT32B0_MAT0 match output 0. |
| 32 | PIO1_7/TXD/CT32B0_MAT1 | bidirectional | 5 V-tolerant general-purpose I/O with pull-up; alternate functions are UART TXD transmitter output and CT32B0_MAT1 match output 1. |
| 33 | VSS | power_in | Exposed heat-sink pad on the package that is connected to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NXP Semicon |
| Package | QFN-32-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (single supply) | VDD | 1.8 | 3.6 | V | single supply (feature list) | 2 | |
| Ambient temperature | Tamb | -40 | 85 | °C | unless otherwise specified (Table 7 header) | 27 | |
| ADC supply voltage | VDD | 2.5 | 3.6 | V | ADC static parameters, ADC sampling frequency 4.5 MHz (Table 8 header) | 30 | |
| ADC maximum sampling frequency | fs | 4.5 | MHz | Tamb = 25 °C, maximum sampling frequency (Table 8 note 7) | 30 | ||
| Internal RC oscillator frequency accuracy | -1 | 1 | % | over full voltage and temperature range | 22 | ||
| Watchdog oscillator frequency variation | -40 | 40 | % | typical frequency variation over operation and temperature, Tamb = −40 °C to +85 °C (Table 15 note 2) | 45 | ||
| System oscillator frequency | 1 | 25 | MHz | system oscillator operating range | 22 | ||
| PLL input clock frequency | 10 | 25 | MHz | PLL input clock range | 22 | ||
| PLL CCO operating frequency | 156 | 320 | MHz | current controlled oscillator (CCO) range | 22 | ||
| PLL output frequency | 100 | MHz | PLL output must be below 100 MHz | 22 | |||
| CPU maximum operating frequency | 50 | MHz | maximum CPU frequency (feature list) | 1 | |||
| XTALIN slave-mode input clock amplitude | 200 | 1000 | mV (RMS) | slave mode, input clock via 100 pF capacitor on XTALIN | 50 | ||
| Maximum output drive current per pin | 20 | mA | per pin (feature list) | 1 | |||
| ADC 10-bit conversion time | 2.44 | μs | 10-bit conversion time | 20 | |||
| RESET low pulse width to reset device | 50 | ns | low-level pulse on RESET resets the device | 24 | |||
| WAKEUP low pulse width to wake from deep power-down | 50 | ns | low pulse on WAKEUP wakes device from deep power-down | 23 | |||
| Nominal I/O and ADC supply voltage | VDD | 3.3 | V | nominal supply for internal regulator and ADC (pin description) | 10 |
CAD (KiCad official)
- Symbol:
LPC1114FHN33 - Footprint:
Package_DFN_QFN:QFN-32-1EP_7x7mm_P0.65mm_EP4.7x4.7mm - 3D model: QFN-32-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
lpc1114fhn33-etched.step/lpc1114fhn33-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lpc1114fhn33.step/lpc1114fhn33.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: NXP Semicon datasheet (60 pp, sha256
7a7c46cf554595c2, retrieved 2026-10-26, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).