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LP873347RHDR

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Texas Instruments DC-DC Converters, VQFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LP873347RHDR

Texas Instruments · DC-DC Converters · VQFN-28-EP(5x5)

LP873347RHDR from Texas Instruments, in a VQFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT_LDO0 power_out LDO0 regulator output; leave the pin floating if LDO0 is not used.
2 FB_B0 input Positive output voltage feedback input for Buck 0.
3 FB_B1 input Positive output voltage feedback input for Buck 1 in two single-phase configuration, and negative output-ground feedback input for Buck 0 in dual-phase configuration.
4 AGND power_in Analog ground.
5 VANA power_in Supply voltage for analog and digital blocks, rated 2.8 V to 5.5 V; must be connected to the same node as VIN_Bx.
6 EN input Programmable enable input for the regulators and GPOs; leave floating if not used.
7 VOUT_LDO1 power_out LDO1 regulator output; leave the pin floating if LDO1 is not used.
8 VIN_LDO1 power_in Power input for LDO1, rated 2.5 V to 5.5 V; connect to VANA if LDO1 is not used.
9 nINT output Open-drain interrupt output, active low; connect to ground if not used.
10 CLKIN bidirectional External clock input, with alternative function as general-purpose digital output GPO2 selected by CLKIN_PIN_SEL; leave floating if not used.
11 VIN_B1 power_in Input for Buck 1; VIN_Bx pins are not connected together internally and must be connected together in the application and locally bypassed.
12 VIN_B1 power_in Input for Buck 1; VIN_Bx pins are not connected together internally and must be connected together in the application and locally bypassed.
13 SW_B1 power_out Buck 1 switch node; leave the pin floating if Buck 1 is not used.
14 SW_B1 power_out Buck 1 switch node; leave the pin floating if Buck 1 is not used.
15 PGND_B1 power_in Power ground for Buck 1.
16 PGND_B1 power_in Power ground for Buck 1.
17 SCL input I2C serial interface clock input; connect a pull-up resistor, or connect to ground if the I2C interface is not used.
18 SDA bidirectional I2C serial interface data input/output; connect a pull-up resistor, or connect to ground if the I2C interface is not used.
19 SGND power_in Signal ground.
20 PGND_B0 power_in Power ground for Buck 0.
21 PGND_B0 power_in Power ground for Buck 0.
22 SW_B0 power_out Buck 0 switch node; leave the pin floating if Buck 0 is not used.
23 SW_B0 power_out Buck 0 switch node; leave the pin floating if Buck 0 is not used.
24 VIN_B0 power_in Input for Buck 0; VIN_Bx pins are not connected together internally and must be connected together in the application and locally bypassed.
25 VIN_B0 power_in Input for Buck 0; VIN_Bx pins are not connected together internally and must be connected together in the application and locally bypassed.
26 GPO output General-purpose digital output; leave the pin floating if not used.
27 PGOOD output Power-good indication output; leave the pin floating if not used.
28 VIN_LDO0 power_in Power input for LDO0, rated 2.5 V to 5.5 V; connect to VANA if LDO0 is not used.
29 THERMAL PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-28-EP(5x5)
Category Power Management (PMIC)
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage on power connections VIN_Bx, VANA (must use the same input supply) VIN_Bx, VANA -0.3 6 V must use the same input supply 5
Voltage on power connections VIN_LDOx VIN_LDOx -0.3 6 V 5
Voltage on buck switch nodes SW_Bx -0.3 V 5
Voltage on buck voltage sense nodes FB_Bx -0.3 V 5
Voltage on LDO output VOUT_LDOx -0.3 V 5
Voltage on logic pins (input or output pins) SDA, SCL, nINT, EN -0.3 6 V 5
Voltage on logic pins (input or output pins) PGOOD, GPO, CLKIN (GPO2) -0.3 V 5
Junction temperature TJ-MAX -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
Maximum lead temperature (soldering, 10 seconds) 260 °C 10 seconds 5
Input voltage range, VIN_Bx and VANA power connections VIN_Bx, VANA 2.8 5.5 V must use the same input supply 5
Voltage on LDO inputs VIN_LDOx 2.5 5.5 V 5
Voltage on logic pins (input or output pins) EN, nINT 0 5.5 V 5
Voltage on logic pins (input pin) CLKIN 0 V 5
Voltage on logic pins (output pins) PGOOD, GPO, GPO2 0 V 5
Voltage on I2C interface, Standard, Fast, Fast+ and High-Speed modes SCL, SDA 0 1.95 V Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz) and High-Speed (3.4 MHz) modes 5
Voltage on I2C interface, Standard, Fast and Fast+ modes SCL, SDA 0 V Standard (100 kHz), Fast (400 kHz) and Fast+ (1 MHz) modes 5
Junction temperature TJ -40 140 °C 5
Ambient temperature TA -40 125 °C 5
Input filtering capacitance for buck regulators CIN_BUCK 1.9 10 µF Effective capacitance, connected from VIN_Bx to PGND_Bx 6
Output filtering capacitance for buck regulators COUT_BUCK 10 22 500 µF Effective capacitance per phase 6
Input filtering capacitance for LDO regulators CIN_LDO 0.6 2.2 µF Effective capacitance, connected from VIN_LDOx to AGND 6
Output filtering capacitance for LDO regulators COUT_LDO 0.4 1 2.7 µF Effective capacitance 6
Input and output capacitor ESR ESRC 2 10 mΩ [1-10] MHz 6
Inductance of the inductor L 0.47 µH 6
Inductance tolerance of the inductor L -30 30 % 6
Input voltage range for buck power inputs V(VIN_Bx), V(VANA) 2.8 3.7 5.5 V VIN_Bx and VANA pins must be connected to the same supply line 6
Output voltage programmable range (buck) VOUT_Bx 0.7 1 3.36 V Programmable voltage range 6
DC output voltage accuracy (buck), force PWM mode VOUT_Bx_DC -20 20 mV Force PWM mode, VOUT < 1 V 7
DC output voltage accuracy (buck), force PWM mode VOUT_Bx_DC -2 2 % Force PWM mode, VOUT ≥ 1 V 7
DC line regulation DCLNR -0.05 0.05 %/V IOUT = 1 A 7
Transient load step response, single-phase output TLDSR -55 55 mV IOUT = 0.1 A to 2 A, TR = TF = 400 ns, PWM mode 7
Transient load step response, dual-phase output TLDSR -50 50 mV IOUT = 0.1 A to 4 A, TR = TF = 400 ns, PWM mode 7
Transient line response (buck) TLNSR -10 10 mV V(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) 7
Forward current limit per phase, programmable range ILIM FWD 1.5 4 A Programmable range 7
Forward current limit accuracy ILIM FWD -5 7.5 20 % V(VIN_Bx) ≥ 3 V, ILIM = 4 A 7
Negative current limit per phase ILIM NEG 1.6 2 3 A 7
On-resistance, high-side FET RDS(ON) HS 50 110 mΩ Each phase, between VIN_Bx and SW_Bx pins (I = 1 A) 7
On-resistance, low-side FET RDS(ON) LS 45 90 mΩ Each phase, between SW_Bx and PGND_Bx pins (I = 1 A) 7
Switching frequency ƒSW 1.8 2 2.2 MHz PWM mode 7
Output pulldown resistance (buck, regulator disabled) RDIS_Bx 150 250 350 Ω Regulator disabled 8
Input voltage range for LDO power inputs VIN_LDOx 2.5 3.7 5.5 V VIN_LDOx can be higher or lower than V(VANA) 8
Output voltage programmable range (LDO) VOUT_LDOx 0.8 3.3 V Programmable voltage range 8
Transient load step response (LDO) TLDSR -50 40 mV IOUT = 1 mA to 300 mA, TR = TF = 1 µs 8
Transient line response (LDO) TLNSR -7 7 mV V(VIN_LDOx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) 8
LDO current limit ISHORT(LDOx) 400 500 600 mA VOUT = 0 V 8
VANA overvoltage threshold, voltage rising VANAOVP 5.6 5.8 6.1 V Voltage rising 9
VANA undervoltage lockout, voltage rising VANAUVLO 2.51 2.63 2.75 V Voltage rising 9
Thermal shutdown, temperature rising 140 150 160 °C Temperature rising 9
Thermal warning, temperature rising 115 125 135 °C Temperature rising, TDIE_WARN_LEVEL = 0 9
Buck short-circuit detection threshold 280 360 440 mV Threshold 9
LDO short-circuit detection threshold 190 300 450 mV Threshold 9
Overvoltage monitoring for PGOOD (LDO), voltage rising VOUT_LDO_DC 106 108 110 % Compared to DC output voltage level, VOUT_LDO_DC 9
Undervoltage monitoring for PGOOD (LDO), voltage falling VOUT_LDO_DC 90 92 94 % Compared to DC output voltage level, VOUT_LDO_DC 9
Thermal resistance, junction-to-ambient RθJA 36.7 °C/W 6
Thermal resistance, junction-to-case (top) RθJCtop 26.6 °C/W 6
Thermal resistance, junction-to-board RθJB 8.9 °C/W 6
Junction-to-top characterization parameter ψJT 0.4 °C/W 6
Junction-to-board characterization parameter ψJB 8.8 °C/W 6
Thermal resistance, junction-to-case (bottom) RθJCbot 2.2 °C/W 6

CAD (KiCad official)

  • Symbol: LP873347RHDR
  • Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • 3D model: VQFN-28-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: lp873347rhdr-etched.step / lp873347rhdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp873347rhdr.step / lp873347rhdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (85 pp, sha256 889456548ab095e4, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF