component

LP87332ARHDRQ1

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, VQFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)lp87332arhdrq1factory-2.0.0extractor-text

Verified LP87332ARHDRQ1

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 29 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LP87332ARHDRQ1 · VQFN-28-EP(5x5) · 29 pins
  • ✓copper: 29 copper pads, none touching another net
  • ✓datasheet: all 29 pin names found in the 78-page datasheet
  • ✓distributor: lcsc C2650302, digikey 296-51414-2-ND, mouser 595-LP87332ARHDRQ1
  • ✓family: QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-75qe8slu/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 29 pins = 29 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 29 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lp87332arhdrq1.kicad_sym✓ lp87332arhdrq1.kicad_mod✓ lp87332arhdrq1.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers lp87332arhdrq1: viewers · Ray 1d ago
lp87332arhdrq1-etched.glb Publish 0.1.0 · Ray 1d ago
lp87332arhdrq1-etched.step lp87332arhdrq1: factory component page (tier=mfr) · Ray 1d ago
lp87332arhdrq1-hero.glb lp87332arhdrq1: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
lp87332arhdrq1-hero.overlay.json Publish 0.1.0 · Ray 1d ago
lp87332arhdrq1.glb Publish 0.1.0 · Ray 1d ago
lp87332arhdrq1.kicad_mod Publish 0.1.0 · Ray 1d ago
lp87332arhdrq1.kicad_sym Publish 0.1.0 · Ray 1d ago
lp87332arhdrq1.lbr Publish 0.1.0 · Ray 1d ago
lp87332arhdrq1.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 29 pins · Ray 1d ago

LP87332ARHDRQ1

Texas Instruments · DC-DC Converters · VQFN-28-EP(5x5)

LP87332ARHDRQ1 from Texas Instruments, in a VQFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT_LDO0 power_out LDO0 output; leave floating if LDO0 is not used.
2 FB_B0 input Positive output-voltage feedback input for Buck 0.
3 FB_B1 input Positive output-voltage feedback input for Buck 1.
4 AGND power_in Ground.
5 VANA power_in Supply voltage for analog and digital blocks; must be connected to the same node as VIN_Bx.
6 EN input Programmable enable signal for regulators and GPOs; leave floating if not used.
7 VOUT_LDO1 power_out LDO1 output; leave floating if LDO1 is not used.
8 VIN_LDO1 power_in Power input for LDO1; connect to VANA if LDO1 is not used.
9 nINT output Open-drain interrupt output, active LOW; connect to ground if not used.
10 CLKIN bidirectional External clock input, alternatively general-purpose digital output GPO2; leave floating if not used.
11 VIN_B1 power_in Input for Buck 1; VIN_Bx pins are not connected together internally and must be connected together externally and locally bypassed.
12 VIN_B1 power_in Input for Buck 1; VIN_Bx pins are not connected together internally and must be connected together externally and locally bypassed.
13 SW_B1 power_out Buck 1 switch node; leave floating if Buck 1 is not used.
14 SW_B1 power_out Buck 1 switch node; leave floating if Buck 1 is not used.
15 PGND_B1 power_in Power ground for Buck 1.
16 PGND_B1 power_in Power ground for Buck 1.
17 SCL input Serial interface clock input for I2C access; connect a pullup resistor, or connect to ground if I2C is not used.
18 SDA bidirectional Serial interface data input and output for I2C access; connect a pullup resistor, or connect to ground if I2C is not used.
19 SGND power_in Ground.
20 PGND_B0 power_in Power ground for Buck 0.
21 PGND_B0 power_in Power ground for Buck 0.
22 SW_B0 power_out Buck 0 switch node; leave floating if Buck 0 is not used.
23 SW_B0 power_out Buck 0 switch node; leave floating if Buck 0 is not used.
24 VIN_B0 power_in Input for Buck 0; VIN_Bx pins are not connected together internally and must be connected together externally and locally bypassed.
25 VIN_B0 power_in Input for Buck 0; VIN_Bx pins are not connected together internally and must be connected together externally and locally bypassed.
26 GPO output General-purpose digital output; leave floating if not used.
27 PGOOD output Power-good indication signal; leave floating if not used.
28 VIN_LDO0 power_in Power input for LDO0; connect to VANA if LDO0 is not used.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-28-EP(5x5)
Category Power Management (PMIC)
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage on power connections (VIN_Bx, VANA) -0.3 6 V Over operating free-air temperature range 5
Voltage on power connections (VIN_LDOx) -0.3 6 V Over operating free-air temperature range 5
Junction temperature TJ-MAX -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
Input voltage on power connections VIN_Bx, VANA 2.8 5.5 V Must use the same input supply 5
Input voltage on LDO inputs VIN_LDOx 2.5 5.5 V Voltage on LDO inputs 5
Voltage on logic pins EN, nINT 0 5.5 V Input or output pins 5
Voltage on I2C interface SCL, SDA 0 1.95 V Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz) and High-Speed (3.4 MHz) modes 5
Junction temperature TJ -40 140 °C 5
Ambient temperature TA -40 125 °C 5
Input filtering capacitance for buck regulators CIN_BUCK 1.9 10 µF Effective capacitance, connected from VIN_Bx to PGND_Bx 6
Output filtering capacitance for buck regulators COUT_BUCK 10 22 500 µF Effective capacitance 6
Buck output capacitance, total (local and POL) COUT-TOTAL_BUCK 500 µF Total output capacitance 6
Input filtering capacitance for LDO regulators CIN_LDO 0.6 2.2 µF Effective capacitance, connected from VIN_LDOx to AGND 6
Output filtering capacitance for LDO regulators COUT_LDO 0.4 1 2.7 µF Effective capacitance 6
Input and output capacitor ESR ESRC 2 10 mΩ [1-10] MHz 6
Inductance tolerance L -30 30 % Inductance of the inductor 6
Input voltage range V(VIN_Bx), V(VANA) 2.8 3.7 5.5 V VIN_Bx and VANA pins must be connected to the same supply line 6
Output voltage programmable range VOUT_Bx 0.7 1 3.36 V Programmable voltage range 6
Output current IOUT_Bx 3 A Output current 6
DC output voltage accuracy VOUT_Bx_DC -20 20 mV Force PWM mode, VOUT < 1 V 7
DC output voltage accuracy VOUT_Bx_DC -2 2 % Force PWM mode, VOUT ≥ 1 V 7
DC output voltage accuracy in PFM mode VOUT_Bx_DC -20 40 mV PFM mode, VOUT < 1 V, the average output voltage level is increased by max. 20 mV 7
DC output voltage accuracy in PFM mode VOUT_Bx_DC -2 % PFM mode, VOUT ≥ 1 V, the average output voltage level is increased by max. 20 mV; printed max is 2% + 20 mV 7
DC line regulation DCLNR -0.05 0.05 %/V IOUT = 1 A 7
Transient load step response TLDSR -55 55 mV IOUT = 0.1 A to 2 A, TR = TF = 400 ns, PWM mode 7
Forward current limit per phase ILIM FWD 1.5 4 A Programmable range 7
Forward current limit accuracy ILIM FWD -5 7.5 20 % V(VIN_Bx) ≥ 3 V, ILIM = 4 A 7
Forward current limit accuracy ILIM FWD -20 7.5 20 % 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 4 A 7
Negative current limit per phase ILIM NEG 1.6 2 3 A 7
On-resistance, high-side FET RDS(ON) HS 50 110 mΩ Each phase, between VIN_Bx and SW_Bx pins (I = 1 A) 7
On-resistance, low-side FET RDS(ON) LS 45 90 mΩ Each phase, between SW_Bx and PGND_Bx pins (I = 1 A) 7
Switching frequency ƒSW 1.8 2 2.2 MHz PWM mode 7
Output pulldown resistance RDIS_Bx 150 250 350 Ω Regulator disabled 7
Overvoltage threshold for PGOOD 39 50 64 mV Compared to DC output voltage level, VVOUT_Bx_DC; VIN_Bx and VANA fixed 3.7 V 8
Undervoltage threshold for PGOOD -53 -40 -29 mV Compared to DC output voltage level, VVOUT_Bx_DC; VIN_Bx and VANA fixed 3.7 V 8
Deglitch time during operation and after voltage change 4 15 µs 8
Buck short-circuit detection threshold 280 360 440 mV Threshold 9
Output voltage programmable range LDO VOUT_LDOx 0.8 3.3 V Programmable voltage range 8
Input voltage range for LDO power inputs VIN_LDOx 2.5 3.7 5.5 V VIN_LDOx can be higher or lower than V(VANA) 8
Output current LDO IOUT_LDOx 300 mA Output current 8
Dropout voltage 200 mV V(VIN_LDOx), V(VOUT_LDOx), IOUT = IOUT(max), programmed output voltage is higher than V(VIN_LDOx) 8
DC output voltage accuracy LDO VOUT_LDO_DC -20 20 mV VOUT < 1 V 8
DC output voltage accuracy LDO VOUT_LDO_DC -2 2 % VOUT ≥ 1 V 8
Transient load step response LDO TLDSR -50 40 mV IOUT = 1 mA to 300 mA, TR = TF = 1 µs 8
LDO current limit ISHORT(LDOx) 400 500 600 mA VOUT = 0 V 8
Output pulldown resistance LDO RDIS_LDOx 150 250 350 Ω Regulator disabled 8
Overvoltage monitoring, voltage rising (LDO) 106 108 110 % Compared to DC output voltage level, VOUT_LDO_DC 8
Undervoltage monitoring, voltage falling (LDO) 90 92 94 % Compared to DC output voltage level, VOUT_LDO_DC 8
External input clock frequency fEXT_CLK 1 24 MHz Nominal frequency 9
Required accuracy from nominal frequency -30 10 % Required accuracy from nominal frequency 9
Thermal warning 115 125 135 °C Temperature rising, TDIE_WARN_LEVEL = 0 9
Thermal shutdown 140 150 160 °C Temperature rising 9
Logic input low level VIL 0.4 V 10
Logic input high level VIH 1.2 V 10
Input filtering capacitance (inductor) typical L 0.47 µH Inductance of the inductor 6
Junction-to-ambient thermal resistance RθJA 36.7 °C/W RHD (VQFN) 28 pins 6
Junction-to-board thermal resistance RθJB 8.9 °C/W RHD (VQFN) 28 pins 6

CAD (KiCad official)

  • Symbol: LP87332ARHDRQ1
  • Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • 3D model: VQFN-28-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: lp87332arhdrq1-etched.step / lp87332arhdrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp87332arhdrq1.step / lp87332arhdrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (78 pp, sha256 ae33204986439254, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF