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LP6312AQVF

LOWPOWER · DC-DC Converters · DFN-10-EP(3x3)

LP6312AQVF from LOWPOWER, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN1 power_in Supply input power for buck converter 1, operating range 2.5V to 5.5V (absolute maximum 6.5V).
2 LX1 output Switch-mode connection to the inductor for buck 1, tied to the drains of the internal main and synchronous power MOSFETs.
3 GND1 power_in Common ground for buck converter 1.
4 EN2 input Chip enable for buck 2, with input low at 0.4V max and input high at 1.4V min.
5 FB2 input Feedback input for buck 2 with 0.6V typical reference voltage, set by an external resistor divider.
6 VIN2 power_in Supply input power for buck converter 2, operating range 2.5V to 5.5V (absolute maximum 6.5V).
7 LX2 output Switch-mode connection to the inductor for buck 2, tied to the drains of the internal main and synchronous power MOSFETs.
8 GND2 power_in Common ground for buck converter 2.
9 EN1 input Chip enable for buck 1, with input low at 0.4V max and input high at 1.4V min.
10 FB1 input Feedback input for buck 1 with 0.6V typical reference voltage, set by an external resistor divider.
11 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer LOWPOWER
Package DFN-10-EP(3x3)
Category Power Supply Chip
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage VINX 2.5 5.5 V 5
Control Circuit Input Voltage VCC 2.5 5.5 V 5
Shutdown Supply Current ISD 0.1 1 μA VEN = 0V 5
UVLO Threshold VUVLO 1.8 2 2.2 V VIN Rising 5
Reference Voltage VREF 0.588 0.6 0.612 V 5
Enable Pin Input Low Voltage VEN-L 0.4 V 5
Enable Pin Input High Voltage VEN-H 1.4 V 5
Quiescent Current IQ 70 μA Non-switching, No Load 5
UVLO Hysteresis VUV-HYST 0.2 V 5
Output Load Current ILOAD 2 A 5
Switching Frequency FSW 1.5 MHz ILOAD = 100mA 5
PMOS Current Limit ILIM-P 3 A 5
PMOS On-Resistance RDS(ON)-P 100 mΩ ILOAD = 100mA 5
NMOS On-Resistance RDS(ON)-N 90 mΩ ILOAD = 100mA 5
Maximum Duty Cycle DMAX 100 % 5
Thermal Shutdown Threshold TOTP 150 ℃ 5
Thermal Shutdown Hysteresis THYST 20 ℃ 5
Input Voltage (VIN1, VIN2) VIN -0.3 6.5 V 4
LX Pin Voltage VLX -0.3 0.3 V max is VINX+0.3V 4
All Other Pins Voltage -0.3 0.3 V max is VINX+0.3V 4
Ambient Temperature Operating Range TA -40 85 °C 4
Maximum Junction Temperature TJ_MAX 150 °C 4
Lead Temperature 260 °C Soldering, 10 sec 4
Storage Temperature Range TS -60 125 °C 4
Power Dissipation PD_MAX 1.5 W DFN-10, TA=25°C 4
Recommended Input Voltage (VIN1, VIN2) VIN 2.5 5.5 V 4
Junction Temperature Range TJ -40 125 °C 4
Thermal Resistance Junction-to-Case θJC 7.5 °C/W DFN-10 4
Thermal Resistance Junction-to-Ambient θJA 65 °C/W DFN-10 4
ESD HBM 2 kV Human Body Mode 4
ESD MM 200 V Machine Mode 4

CAD (KiCad official)

  • Symbol: LP6312AQVF
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: lp6312aqvf-etched.step / lp6312aqvf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp6312aqvf.step / lp6312aqvf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LOWPOWER datasheet (12 pp, sha256 3d696f44fcbc0337, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF