# LP5996SD-3333

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-10-EP(3x3)

LP5996SD-3333 from Texas Instruments, in a WSON-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Voltage supply input with a 2.0V to 6.0V operating range; connect a 1µF capacitor between this pin and GND. |
| 2 | EN1 | input | Active-high enable input for regulator 1 (high = on, low = off), with VIL of 0.4V max and VIH of 0.95V min. |
| 3 | EN2 | input | Active-high enable input for regulator 2 (high = on, low = off), with VIL of 0.4V max and VIH of 0.95V min. |
| 4 | CBYP | passive | Internal voltage reference bypass; a 10nF capacitor to GND reduces noise and improves line transient and PSRR, and the pin may be left open. |
| 5 | N/C | unconnected | No connection; do not connect to any other pin. |
| 6 | GND | power_in | Common ground pin; connect externally to the exposed pad. |
| 7 | N/C | unconnected | No connection; do not connect to any other pin. |
| 8 | N/C | unconnected | No connection; do not connect to any other pin. |
| 9 | VOUT2 | power_out | Output of regulator 2 with 300mA maximum current; connect a 1µF capacitor between this pin and GND. |
| 10 | VOUT1 | power_out | Output of regulator 1 with 150mA maximum current; connect a 1µF capacitor between this pin and GND. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-10-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 2 |  | 6 | V |  | 4 |
| Output Voltage Tolerance (25°C) | ΔVOUT | -2.5 |  | 2.5 | % | IOUT = 1mA, 1.5V < VOUT ≤ 3.3V | 4 |
| Output Voltage Tolerance (over temperature) | ΔVOUT | -3.75 |  | 3.75 | % | IOUT = 1mA, 1.5V < VOUT ≤ 3.3V, TJ -40 to +125°C | 4 |
| Line Regulation Error |  |  | 0.03 | 0.3 | %/V | VIN = (VOUT(NOM) + 1.0V) to 6.0V | 4 |
| Load Regulation Error LDO1 |  |  | 85 | 155 | µV/mA | IOUT = 1mA to 150mA (LDO 1) | 4 |
| Load Regulation Error LDO2 |  |  | 26 | 85 | µV/mA | IOUT = 1mA to 300mA (LDO 2) | 4 |
| Dropout Voltage LDO1 | VDO |  | 110 | 220 | mV | IOUT = 1mA to 150mA (LDO 1) | 4 |
| Dropout Voltage LDO2 | VDO |  | 210 | 550 | mV | IOUT = 1mA to 300mA (LDO 2) | 4 |
| Quiescent Current, LDO1 ON, LDO2 ON, no load | IQ |  | 35 | 100 | µA | IOUT1 = IOUT2 = 0mA | 4 |
| Quiescent Current, LDO1 ON, LDO2 OFF | IQ |  | 45 | 110 | µA | IOUT1 = 150mA | 4 |
| Quiescent Current, LDO1 OFF, LDO2 ON | IQ |  | 45 | 110 | µA | IOUT2 = 300mA | 4 |
| Quiescent Current, LDO1 ON, LDO2 ON, full load | IQ |  | 70 | 170 | µA | IOUT1 = 150mA, IOUT2 = 300mA | 4 |
| Shutdown Quiescent Current | IQ |  | 0.5 | 10 | nA | VEN1 = VEN2 = 0.4V | 4 |
| Short Circuit Current Limit LDO1 | ISC |  | 420 | 750 | mA | LDO 1 | 4 |
| Short Circuit Current Limit LDO2 | ISC |  | 550 | 840 | mA | LDO 2 | 4 |
| Maximum Output Current LDO1 | IOUT |  | 150 |  | mA | LDO 1 | 4 |
| Maximum Output Current LDO2 | IOUT |  | 300 |  | mA | LDO 2 | 4 |
| Input Current at VEN1 or VEN2, low | IEN |  | 0.005 | 0.1 | µA | VEN = 0.0V | 5 |
| Input Current at VEN1 or VEN2, high | IEN |  | 2 | 5 | µA | VEN = 6V | 5 |
| Low Input Threshold | VIL |  | 0.4 | 0.4 | V |  | 5 |
| High Input Threshold | VIH | 0.95 | 0.95 |  | V |  | 5 |
| Turn On Time | TON |  | 300 |  | µs | To 95% Level, CBYP = 10nF | 5 |
| Output Capacitance | COUT | 0.7 | 1 |  | µF | Recommended capacitor, X7R | 5 |
| Output Capacitor ESR | ESR | 5 |  | 500 | mΩ |  | 5 |
| Input Voltage | VIN | -0.3 |  | 6.5 | V | Voltage to GND | 3 |
| VOUT1, VOUT2, EN1, EN2 Voltage to GND |  | -0.3 |  | 6.5 | V | Max 6.5V, or VIN + 0.3V | 3 |
| Junction Temperature | TJ-MAX |  |  | 150 | °C |  | 3 |
| Lead/Pad Temperature |  |  |  | 235 | °C |  | 3 |
| Storage Temperature |  | -65 |  | 150 | °C |  | 3 |
| ESD Human Body Model |  |  |  | 2 | kV | 100pF through 1.5kΩ | 3 |
| ESD Machine Model |  |  |  | 200 | V | 200pF | 3 |
| EN1, EN2 Voltage |  | 0 |  | 6 | V | Max 6.0V, or VIN + 0.3V | 3 |
| Junction Temperature Operating Range | TJ | -40 |  | 125 | °C |  | 4 |
| Ambient Temperature Range | TA | -40 |  | 85 | °C |  | 4 |
| Junction To Ambient Thermal Resistance, SON-10 | θJA |  | 55 |  | °C/W | SON-10 package | 4 |

## CAD (KiCad official)

- Symbol: `LP5996SD-3333`
- Footprint: `Package_SON:VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm`
- 3D model: WSON-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `lp5996sd-3333-etched.step` / `lp5996sd-3333-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lp5996sd-3333.step` / `lp5996sd-3333.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/lp5996.pdf) (18 pp, sha256 `a0921df1317b5b75`, retrieved 2026-11-06, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lp5996sd-3333-datasheet.pdf)