component
LP5951MG-1.8
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownLP5951MG-1.8
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SC-70-5
LP5951MG-1.8 from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input voltage 1.8 V to 5.5 V. |
| 2 | GND | power_in | Ground. |
| 3 | EN | input | Enable pin logic input: Low = shutdown, High = normal operation, and this pin should not be left floating. |
| 4 | NC | unconnected | No internal connection. |
| 5 | OUT | power_out | Regulated output voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SC-70-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IN pin voltage to GND | VIN | -0.3 | 6.5 | V | 4 | ||
| EN pin voltage to GND | VEN | -0.3 | 6.5 | V | upper limit is the lower of VIN + 0.3 V or 6.5 V | 4 | |
| Junction temperature (TJ-MAX) | TJ | 150 | °C | 4 | |||
| Package peak reflow temperature (10-20 s) | 240 | °C | 4 | ||||
| Package peak reflow temperature (Pb-free, 10-20 s) | 260 | °C | 4 | ||||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Input voltage | VIN | 1.8 | 5.5 | V | 4 | ||
| Enable input voltage | VEN | 0 | V | maximum is VIN + 0.3 V | 4 | ||
| Junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Output voltage tolerance | -2 | 2 | % | IOUT = 1 mA, TJ = 25°C | 5 | ||
| Output voltage tolerance | -3.5 | 3.5 | % | IOUT = 1 mA, -30°C ≤ TJ ≤ +125°C | 5 | ||
| Line regulation error | 0.1 | %/V | VIN = VOUT(NOM) + 1 V to 5.5 V | 5 | |||
| Load regulation error | -0.01 | %/mA | IOUT = 1 mA to 150 mA | 5 | |||
| Output voltage dropout | VDO | 200 | 350 | mV | IOUT = 150 mA, VOUT < 2.5 V | 5 | |
| Quiescent current | IQ | 29 | 55 | µA | VEN = 0.9 V, ILOAD = 0 | 5 | |
| Quiescent current | IQ | 33 | 70 | µA | VEN = 0.9 V, ILOAD = 150 mA | 5 | |
| Quiescent current in shutdown | IQ | 0.005 | 1 | µA | VEN = 0 V, TJ = 25°C | 5 | |
| Output current (short circuit) | ISC | 150 | 400 | mA | VIN = VOUT(NOM) + 1 V | 5 | |
| Maximum input current at EN | IEN | -1 | 1 | µA | 0 V ≤ VEN ≤ VIN, VIN = 5.5 V, -40°C ≤ TJ ≤ 125°C | 6 | |
| Low input threshold (shutdown) | VIL | 0.4 | V | VIN = 1.8 V to 5.5 V, -40°C ≤ TJ ≤ 125°C | 6 | ||
| Dynamic line transient | ΔVOUT | -2 | 2 | mV | VIN = VOUT(NOM) + 1 V to VOUT(NOM) + 1 V + 0.6 V in 30 µs, no load | 5 | |
| Dynamic load transient | ΔVOUT | -30 | mV | IOUT = 0 mA to 150 mA in 10 µs | 5 | ||
| Dynamic load transient | ΔVOUT | 20 | mV | IOUT = 150 mA to 0 mA in 10 µs | 5 | ||
| Dynamic load transient | ΔVOUT | -50 | mV | IOUT = 1 mA to 150 mA in 1 µs | 5 | ||
| Dynamic load transient | ΔVOUT | 40 | mV | IOUT = 150 mA to 1 mA in 1 µs | 5 | ||
| Overshoot on start-up | ΔVOUT | 10 | mV | Nominal conditions | 5 | ||
| Output capacitance | COUT | 0.7 | 1 | 47 | µF | IOUT = 150 mA, VIN = 5 V | 6 |
| Output capacitor ESR | ESR | 0.003 | 0.3 | Ω | IOUT = 150 mA, VIN = 5 V | 6 | |
| Thermal shutdown | TSD | 160 | °C | 5 | |||
| Temperature hysteresis | 20 | °C | 5 | ||||
| Power supply rejection ratio | PSRR | 60 | dB | sine modulated VIN, f = 100 Hz | 5 | ||
| Power supply rejection ratio | PSRR | 50 | dB | sine modulated VIN, f = 10 kHz | 5 | ||
| Output noise | EN | 125 | µVRMS | BW = 10 Hz - 100 kHz | 5 | ||
| Turnon time | TON | 30 | µs | IOUT = 1 mA | 5 | ||
| Junction-to-ambient thermal resistance (SC70) | RθJA | 276.7 | °C/W | SC70 (DCK) 5 pins | 4 | ||
| Junction-to-case (top) thermal resistance (SC70) | RθJC(top) | 86.3 | °C/W | SC70 (DCK) 5 pins | 4 | ||
| Junction-to-board thermal resistance (SC70) | RθJB | 56.9 | °C/W | SC70 (DCK) 5 pins | 4 | ||
| Junction-to-top characterization parameter (SC70) | ψJT | 1.3 | °C/W | SC70 (DCK) 5 pins | 4 | ||
| Junction-to-board characterization parameter (SC70) | ψJB | 56.1 | °C/W | SC70 (DCK) 5 pins | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | LP5951 ground pin using as wide, and as short, of a copper trace as is practical. | 14 |
CAD (KiCad official)
- Symbol:
LP5951MG-1.8 - Footprint:
Package_TO_SOT_SMD:SOT-353_SC-70-5 - 3D model: SC-70-5 (KiCad packages3D, STEP)
- 3D model files:
lp5951mg-1-8-etched.step/lp5951mg-1-8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lp5951mg-1-8.step/lp5951mg-1-8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
a6d29ed11a16f367, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).