component
LP5912Q1.8DRVTQ1
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownLP5912Q1.8DRVTQ1
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)
LP5912Q1.8DRVTQ1 from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage, fixed from 0.8 V to 5.5 V in 25-mV steps per the voltage options. |
| 2 | NC | unconnected | No internal connection; leave open or connect to ground. |
| 3 | PG | output | Power-good indicator output that requires an external pullup. |
| 4 | EN | input | Enable input: logic high turns the device on and logic low turns it off, with an internal 3-MΩ pulldown. |
| 5 | GND | power_in | Ground reference pin for the device. |
| 6 | IN | power_in | Unregulated input voltage supply to the regulator. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage tolerance | ΔVOUT | -3 | 3 | % | For 1.1 V ≤ VOUT(NOM) < 3.3 V: VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V, IOUT = 1 mA to 500 mA | 5 | |
| Input supply voltage | VIN | 1.6 | 6.5 | V | 4 | ||
| Output voltage | VOUT | 0.8 | 5.5 | V | 4 | ||
| Enable input voltage | VEN | 0 | V | max is VIN | 4 | ||
| PG pin OFF voltage | VPG | 0 | 6.5 | V | 4 | ||
| Output current | IOUT | 0 | 500 | mA | 4 | ||
| Operating junction temperature | TJ-MAX-OP | -40 | 125 | °C | 4 | ||
| Input voltage | VIN | -0.3 | 7 | V | 4 | ||
| Output voltage | VOUT | -0.3 | 7 | V | 4 | ||
| Enable input voltage | VEN | -0.3 | 7 | V | 4 | ||
| Power Good (PG) pin OFF voltage | VPG | -0.3 | 7 | V | 4 | ||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Line regulation | 0.8 | %/V | VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V (VOUT(NOM) ≥ 1.1 V) | 5 | |||
| Load regulation | 0.0022 | %/mA | IOUT = 1 mA to 500 mA | 5 | |||
| Short-circuit current limit | ISC | 700 | 900 | 1100 | mA | TJ = 25°C | 5 |
| Reverse leakage current | IRO | 10 | 150 | µA | VIN < VOUT | 5 | |
| Quiescent current | IQ | 30 | 55 | µA | VEN = 1.3 V, IOUT = 0 mA | 5 | |
| Quiescent current | IQ | 400 | 600 | µA | VEN = 1.3 V, IOUT = 500 mA | 5 | |
| Quiescent current, shutdown mode | IQ(SD) | 0.2 | 1.5 | µA | VEN = 0 V, -40°C ≤ TJ ≤ 85°C | 5 | |
| Quiescent current, shutdown mode | IQ(SD) | 0.2 | 5 | µA | VEN = 0 V | 5 | |
| Ground current | IG | 35 | µA | VEN = 1.3 V, IOUT = 0 mA | 5 | ||
| Dropout voltage | VDO | 170 | 250 | mV | IOUT = 500 mA, 1.6 V ≤ VOUT(NOM) < 3.3 V | 5 | |
| Power Supply Rejection Ratio | PSRR | 80 | dB | f = 100 Hz, VOUT ≥ 1.1 V, IOUT = 20 mA | 6 | ||
| Power Supply Rejection Ratio | PSRR | 75 | dB | f = 1 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA | 6 | ||
| Power Supply Rejection Ratio | PSRR | 65 | dB | f = 10 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA | 6 | ||
| Power Supply Rejection Ratio | PSRR | 40 | dB | f = 100 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA | 6 | ||
| Noise voltage | eN | 12 | µVRMS | IOUT = 1 mA, BW = 10 Hz to 100 kHz | 6 | ||
| Thermal shutdown temperature | TSD | 160 | °C | 6 | |||
| Thermal shutdown hysteresis | THYS | 15 | °C | 6 | |||
| OFF threshold | VEN(OFF) | 0.3 | V | VIN = 1.6 V to 6.5 V, VEN falling until device is disabled | 6 | ||
| ON threshold | VEN(ON) | 1.3 | V | 1.6 V ≤ VIN ≤ 6.5 V, VEN rising until device is enabled | 6 | ||
| Input current at EN pin | IEN | 2.5 | µA | VEN = 6.5 V, VIN = 6.5 V | 6 | ||
| PG high threshold (% of nominal VOUT) | PGHTH | 94 | % | 6 | |||
| PG low threshold (% of nominal VOUT) | PGLTH | 90 | % | 6 | |||
| PG pin low-level output voltage | VOL(PG) | 100 | mV | VOUT < PGLTH, sink current = 1 mA | 6 | ||
| PG pin leakage current | IlKG(PG) | 1 | µA | VOUT < PGHTH, VPG = 6.5 V | 6 | ||
| PG delay time | tPGD | 140 | µs | Time from VOUT > PG threshold to PG toggling | 6 | ||
| Line transients (VIN rising) | ΔVOUT | 1 | mV | VIN = (VOUT(NOM) + 0.5 V) to (VOUT(NOM) + 1.1 V), VIN trise = 30 µs | 7 | ||
| Line transients (VIN falling) | ΔVOUT | -1 | mV | VIN = (VOUT(NOM) + 1.1 V) to (VOUT(NOM) + 0.5 V), VIN tfall = 30 µs | 7 | ||
| Load transients (IOUT rising) | ΔVOUT | -45 | mV | IOUT = 5 mA to 500 mA, IOUT trise = 10 µs | 7 | ||
| Load transients (IOUT falling) | ΔVOUT | 45 | mV | IOUT = 500 mA to 5 mA, IOUT tfall = 10 µs | 7 | ||
| Overshoot on start-up | 5 | % | Stated as a percentage of VOUT(NOM) | 7 | |||
| Turnon time | tON | 200 | µs | From VEN > VEN(ON) to VOUT = 95% of VOUT(NOM) | 7 | ||
| Output discharge pulldown resistance | RAD | 100 | Ω | VEN = 0 V, VIN = 3.6 V | 7 | ||
| Input capacitance | CIN | 0.7 | 1 | µF | Capacitance for stability | 7 | |
| Output capacitance | COUT | 0.7 | 1 | 10 | µF | 7 | |
| Output ESR | ESR | 5 | 500 | mΩ | 7 | ||
| Junction-to-ambient thermal resistance, High-K | RθJA | 71.2 | °C/W | High-K PCB per JESD51-7 | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 93.7 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 40.7 | °C/W | 4 | |||
| Junction-to-top characterization parameter | ψJT | 2.5 | °C/W | 4 | |||
| Junction-to-board characterization parameter | ψJB | 41.1 | °C/W | 4 | |||
| Junction-to-case (bottom) thermal resistance | ψJC(bot) | 11.2 | °C/W | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | ground pin using as wide and as short of a copper trace as is practical. | 24 |
CAD (KiCad official)
- Symbol:
LP5912Q1.8DRVTQ1 - Footprint:
Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm - 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
lp5912q1-8drvtq1-etched.step/lp5912q1-8drvtq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lp5912q1-8drvtq1.step/lp5912q1-8drvtq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (35 pp, sha256
34118b388e5edb0e, retrieved 2026-11-06, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).