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LP5912Q1.2DRVRQ1

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Texas Instruments Linear Voltage Regulators (LDO), WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LP5912Q1.2DRVRQ1

Texas Instruments · Linear Voltage Regulators (LDO) · WSON-6-EP(2x2)

LP5912Q1.2DRVRQ1 from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated output voltage (fixed 1.2 V for this option; output range of the family is 0.8 V to 5.5 V, up to 500 mA).
2 NC unconnected No internal connection; leave open, or connect to ground.
3 PG output Open-drain power-good indicator that requires an external pullup (10 kΩ to 100 kΩ recommended) with typical 140 µs delay, and rated 0 V to 6.5 V when off.
4 EN input Enable input: logic high turns the device on, logic low turns it off, with internal 3-MΩ pulldown, and valid range 0 V to VIN.
5 GND power_in Ground.
6 IN power_in Unregulated input voltage, recommended operating range 1.6 V to 6.5 V.
7 Thermal Pad passive Exposed thermal pad: connect to copper area under the package for thermal performance, with thermal vias recommended; connect to ground or leave floating, and not to any other potential.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-6-EP(2x2)
Category Power Supply Chip
Pins 7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage tolerance ΔVOUT -3 3 % 1.1 V ≤ VOUT(NOM) < 3.3 V: VOUT(NOM)+0.5 V ≤ VIN ≤ 6.5 V, IOUT = 1 mA to 500 mA 5
Line regulation 0.8 %/V VOUT(NOM) ≥ 1.1 V: VOUT(NOM)+0.5 V ≤ VIN ≤ 6.5 V 5
Load regulation 0.0022 %/mA IOUT = 1 mA to 500 mA 5
Short-circuit current limit ISC 700 900 1100 mA TJ = 25°C 5
Reverse leakage current IRO 10 150 µA VIN < VOUT 5
Quiescent current, no load IQ 30 55 µA VEN = 1.3 V, IOUT = 0 mA 5
Quiescent current, 500 mA load IQ 400 600 µA VEN = 1.3 V, IOUT = 500 mA 5
Shutdown quiescent current IQ(SD) 0.2 1.5 µA VEN = 0 V, -40°C ≤ TJ ≤ 85°C 5
Shutdown quiescent current IQ(SD) 0.2 5 µA VEN = 0 V 5
Ground current IG 35 µA VEN = 1.3 V, IOUT = 0 mA 5
PSRR 100 Hz PSRR 80 dB f = 100 Hz, VOUT ≥ 1.1 V, IOUT = 20 mA 6
PSRR 1 kHz PSRR 75 dB f = 1 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA 6
PSRR 10 kHz PSRR 65 dB f = 10 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA 6
PSRR 100 kHz PSRR 40 dB f = 100 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA 6
Output noise voltage eN 12 µVRMS IOUT = 1 mA, BW = 10 Hz to 100 kHz 6
Thermal shutdown temperature TSD 160 °C 6
Thermal shutdown hysteresis THYS 15 °C 6
EN OFF threshold VEN(OFF) 0.3 V VIN = 1.6 V to 6.5 V, VEN falling until device is disabled 6
EN ON threshold VEN(ON) 1.3 V 1.6 V ≤ VIN ≤ 6.5 V, VEN rising until device is enabled 6
EN pin input current IEN 2.5 µA VEN = 6.5 V, VIN = 6.5 V 6
EN pin input current IEN 0.001 µA VEN = 0 V, VIN = 3.3 V 6
PG high threshold PGHTH 94 % of nominal VOUT 6
PG low threshold PGLTH 90 % of nominal VOUT 6
PG pin low-level output voltage VOL(PG) 100 mV VOUT < PGLTH, sink current = 1 mA 6
PG pin leakage current IlKG(PG) 1 µA VOUT < PGHTH, VPG = 6.5 V 6
PG delay time tPGD 140 µs Time from VOUT > PG threshold to PG toggling 6
Line transient, VIN rising ΔVOUT 1 mV VIN = (VOUT(NOM)+0.5 V) to (VOUT(NOM)+1.1 V), VIN trise = 30 µs 7
Line transient, VIN falling ΔVOUT -1 mV VIN = (VOUT(NOM)+1.1 V) to (VOUT(NOM)+0.5 V), VIN tfall = 30 µs 7
Load transient, rising ΔVOUT -45 mV IOUT = 5 mA to 500 mA, IOUT trise = 10 µs 7
Load transient, falling ΔVOUT 45 mV IOUT = 500 mA to 5 mA, IOUT tfall = 10 µs 7
Overshoot on start-up 5 % Stated as a percentage of VOUT(NOM) 7
Turnon time tON 200 µs From VEN > VEN(ON) to VOUT = 95% of VOUT(NOM) 7
Output discharge pulldown resistance RAD 100 Ω VEN = 0 V, VIN = 3.6 V 7
Input capacitance CIN 0.7 1 µF Capacitance for stability 7
Output capacitance COUT 0.7 1 10 µF Capacitance for stability 7
Output capacitor ESR ESR 5 500 mΩ 7
Input voltage (abs max) VIN -0.3 7 V 4
Output voltage (abs max) VOUT -0.3 7 V 4
Enable input voltage (abs max) VEN -0.3 7 V 4
PG pin OFF voltage (abs max) VPG -0.3 7 V 4
Junction temperature (abs max) TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Input supply voltage VIN 1.6 6.5 V 4
Output voltage range VOUT 0.8 5.5 V 4
Enable input voltage VEN 0 V Max is VIN 4
PG pin OFF voltage VPG 0 6.5 V 4
Output current IOUT 0 500 mA 4
Operating junction temperature TJ-MAX-OP -40 125 °C 4
HBM ESD V(ESD) -2000 2000 V Human-body model, per AEC Q100-002 4
CDM ESD V(ESD) -1000 1000 V Charged-device model, per AEC Q100-011 4
Junction-to-ambient thermal resistance RθJA 71.2 °C/W DRV (WSON) 6 pins, High-K 4
Junction-to-case (top) thermal resistance RθJC(top) 93.7 °C/W 4
Junction-to-board thermal resistance RθJB 40.7 °C/W 4
Junction-to-case (bottom) thermal resistance ψJC(bot) 11.2 °C/W 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper ground pin using as wide and as short of a copper trace as is practical. 24

CAD (KiCad official)

  • Symbol: LP5912Q1.2DRVRQ1
  • Footprint: Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: lp5912q1-2drvrq1-etched.step / lp5912q1-2drvrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp5912q1-2drvrq1.step / lp5912q1-2drvrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 6f09792344f18d7a, retrieved 2026-10-23, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF