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LP5912-3.0DRVR

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)lp5912-3.0drvrfactory-2.0.0extractor-text

Verified LP5912-3.0DRVR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 7 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LP5912-3.0DRVR · WSON-6-EP(2x2) · 7 pins
  • ✓copper: 7 copper pads, none touching another net
  • ✓datasheet: all 7 pin names found in the 38-page datasheet
  • ✓distributor: lcsc C2869554, digikey 296-48608-2-ND, mouser 595-LP5912-3.0DRVR
  • ✓family: WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ib9xvsz8/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 7 pins = 7 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 7 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lp5912-3-0drvr.kicad_sym✓ lp5912-3-0drvr.kicad_mod✓ lp5912-3-0drvr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers lp5912-3-0drvr: viewers · Ray 1d ago
lp5912-3-0drvr-etched.glb Publish 0.1.0 · Ray 1d ago
lp5912-3-0drvr-etched.step lp5912-3-0drvr: factory component page (tier=mfr) · Ray 1d ago
lp5912-3-0drvr-hero.glb lp5912-3-0drvr: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
lp5912-3-0drvr-hero.overlay.json Publish 0.1.0 · Ray 1d ago
lp5912-3-0drvr.glb Publish 0.1.0 · Ray 1d ago
lp5912-3-0drvr.kicad_mod Publish 0.1.0 · Ray 1d ago
lp5912-3-0drvr.kicad_sym Publish 0.1.0 · Ray 1d ago
lp5912-3-0drvr.lbr Publish 0.1.0 · Ray 1d ago
lp5912-3-0drvr.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 7 pins · Ray 1d ago

LP5912-3.0DRVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)

LP5912-3.0DRVR from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated output voltage; the device supplies up to 500 mA with a fixed output from 0.8 V to 5.5 V.
2 NC unconnected No internal connection; leave open, or connect to ground.
3 PG output Power-good open-drain indicator that requires an external pullup, typically 10 kΩ to 100 kΩ, and whose status is undefined when VIN is below 1.6 V.
4 EN input Enable input; logic high turns the device on and logic low turns it off, with an internal 3-MΩ pulldown to GND.
5 GND power_in Ground.
6 IN power_in Unregulated input voltage with a recommended supply range of 1.6 V to 6.5 V.
7 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-6-EP(2x2)
Category Power Management (PMIC)
Pins 7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN -0.3 7 V 4
Output voltage VOUT -0.3 7 V 4
Enable input voltage VEN -0.3 7 V 4
Power Good pin OFF voltage VPG -0.3 7 V 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Input supply voltage VIN 1.6 6.5 V 4
Output voltage VOUT 0.8 5.5 V 4
Enable input voltage VEN 0 V Upper limit printed as VIN 4
PG pin OFF voltage VPG 0 6.5 V 4
Output current IOUT 0 500 mA 4
Operating junction temperature TJ-MAX-OP -40 125 °C 4
Output voltage tolerance ΔVOUT -3 3 % For 1.1 V ≤ VOUT(NOM) < 3.3 V: VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V, IOUT = 1 mA to 500 mA 5
Line regulation 0.8 %/V For VOUT(NOM) ≥ 1.1 V: VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V 5
Short-circuit current limit ISC 700 900 1100 mA TJ = 25°C 5
Reverse leakage current IRO 10 150 µA VEN = VIN = 0 V, VOUT = 5.5 V 5
Quiescent current IQ 30 55 µA VEN = 1.3 V, IOUT = 0 mA 5
Quiescent current at full load IQ 400 600 µA VEN = 1.3 V, IOUT = 500 mA 5
Quiescent current, shutdown mode IQ(SD) 0.2 1.5 µA VEN = 0 V, -40°C ≤ TJ ≤ 85°C 5
Quiescent current, shutdown mode IQ(SD) 0.2 5 µA VEN = 0 V 5
Ground current IG 35 µA VEN = 1.3 V, IOUT = 0 mA 5
Dropout voltage VDO 170 250 mV IOUT = 500 mA, 1.6 V ≤ VOUT(NOM) < 3.3 V 5
Dropout voltage VDO 95 180 mV IOUT = 500 mA, 3.3 V ≤ VOUT(NOM) ≤ 5.5 V 5
Noise voltage eN 12 µVRMS IOUT = 1 mA, BW = 10 Hz to 100 kHz 6
Thermal shutdown temperature TSD 160 °C 6
Thermal shutdown hysteresis THYS 15 °C 6
OFF threshold VEN(OFF) 0.3 V VIN = 1.6 V to 6.5 V, VEN falling until device is disabled 6
ON threshold VEN(ON) 1.3 V 1.6 V ≤ VIN ≤ 6.5 V, VEN rising until device is enabled 6
Input current at EN pin IEN 2.5 µA VEN = 6.5 V, VIN = 6.5 V 6
PG high threshold (% of nominal VOUT) PGHTH 94 % 6
PG low threshold (% of nominal VOUT) PGLTH 90 % 6
PG pin low-level output voltage VOL(PG) 100 mV VOUT < PGLTH, sink current = 1 mA 6
PG pin leakage current IlKG(PG) 1 µA VOUT < PGHTH, VPG = 6.5 V 6
PG delay time tPGD 140 µs Time from VOUT > PG threshold to PG toggling 6
Line transients ΔVOUT -1 1 mV VIN trise/tfall = 30 µs, VOUT(NOM) ≥ 1.1 V 7
Load transients ΔVOUT -45 45 mV IOUT = 5 mA to 500 mA, trise = 10 µs 7
Overshoot on start-up 5 % Stated as a percentage of VOUT(NOM) 7
Turnon time tON 200 µs Time from VEN > VEN(ON) to VOUT = 95% of VOUT(NOM) 7
Output discharge pull-down resistance RAD 100 Ω VEN = 0 V, VIN = 3.6 V 7
Input capacitance CIN 0.7 1 µF Capacitance for stability 7
Output capacitance COUT 0.7 1 10 µF Capacitance for stability 7
Output voltage ESR ESR 5 500 mΩ 7
Junction-to-ambient thermal resistance, High-K RθJA 71.2 °C/W DRV (WSON) 6-pin, High-K board 4
Junction-to-case (top) thermal resistance RθJC(top) 93.7 °C/W DRV (WSON) 6-pin 4
Junction-to-board thermal resistance RθJB 40.7 °C/W DRV (WSON) 6-pin 4
Junction-to-case (bottom) thermal resistance RJC(bot) 11.2 °C/W DRV (WSON) 6-pin 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper ground pin using as wide and as short of a copper trace as is practical. 24

CAD (KiCad official)

  • Symbol: LP5912-3.0DRVR
  • Footprint: Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: lp5912-3-0drvr-etched.step / lp5912-3-0drvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp5912-3-0drvr.step / lp5912-3-0drvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 de84246f830e2a08, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF