component
LP5910-1.8DRVT
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownLP5910-1.8DRVT
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)
LP5910-1.8DRVT from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Voltage output; a 1-µF low-ESR capacitor must be connected from this pin to the GND pin, and the output connects to the load circuit. |
| 2 | NC | unconnected | No internal connection; connect to ground or leave open. |
| 3 | NC | unconnected | No internal connection; connect to ground or leave open. |
| 4 | EN | input | Enable input; the regulator is disabled when logic low and enabled when logic high, with an internal 1-MΩ pull-down resistor to ground. |
| 5 | GND | power_in | Common ground; the exposed thermal pad must be connected to this same ground potential and to no other potential. |
| 6 | IN | power_in | Voltage supply input; a 1-µF capacitor must be connected at this input. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage tolerance | ΔVOUT | -2 | 2 | %VOUT | VIN = (VOUT(NOM) + 0.5 V) to 3.3 V, IOUT = 1 mA to 300 mA | 5 | |
| Input voltage absolute maximum | VIN | -0.3 | 3.6 | V | 4 | ||
| Output voltage absolute maximum | VOUT | -0.3 | 3.6 | V | 4 | ||
| Enable input voltage absolute maximum | VEN | -0.3 | 3.6 | V | 4 | ||
| Electrostatic discharge HBM | V(ESD) | -1000 | 1000 | V | Human-body model, per ANSI/ESDA/JEDEC JS-001 | 4 | |
| Electrostatic discharge CDM | V(ESD) | -250 | 250 | V | Charged-device model, per JEDEC JESD22-C101 | 4 | |
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Junction temperature absolute maximum | TJ(MAX) | 150 | °C | 4 | |||
| Input voltage | VIN | 1.3 | 3.3 | V | 4 | ||
| Output voltage | VOUT | 0.8 | 2.3 | V | 4 | ||
| Enable input voltage | VEN | 0 | 3.3 | V | 4 | ||
| Output current | IOUT | 0 | 300 | mA | 4 | ||
| Junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Ambient temperature | TA | -40 | 85 | °C | 4 | ||
| Load current | ILOAD | 0 | 300 | mA | See note (4) | 5 | |
| Dropout voltage 1.8 V <= VOUT <= 2.3 V | VDO | 145 | 220 | mV | IOUT = 300 mA, WSON only | 5 | |
| Output current limit | ILIMIT | 450 | mA | VOUT = VOUT(NOM) - 0.1 V, VIN = VOUT(NOM) + 0.5 V | 5 | ||
| Output reverse current | IRO | -20 | 0 | µA | VOUT = 3.3 V, VIN = VEN = 0 V, VOUT > VIN | 5 | |
| Output reverse current | IRO | 0 | 50 | µA | VOUT = 3.3 V, VIN = VEN = 1.3 V, VOUT > VIN | 5 | |
| EN low threshold (Off) | VIL | 0.3 | V | VIN = 1.3 V to 3.3 V | 6 | ||
| EN high threshold (On) | VIH | 1 | V | 6 | |||
| Line transient, rising input | ΔVOUT | 0 | 1 | mV | VIN = (VOUT(NOM) + 0.5 V) to (VOUT(NOM) + 1 V) in 30 µs, IOUT = 1 mA | 6 | |
| Line transient, falling input | ΔVOUT | -1 | 0 | mV | VIN = (VOUT(NOM) + 1 V) to (VOUT(NOM) + 0.5 V) in 30 µs, IOUT = 1 mA | 6 | |
| Load transient, load step up | ΔVOUT | -45 | mV | IOUT = 1 mA to 100 mA in 10 µs | 6 | ||
| Load transient, load step down | ΔVOUT | 45 | mV | IOUT = 100 mA to 1 mA in 10 µs | 6 | ||
| Output voltage tolerance (line regulation) | 0.01 | %/V | VIN = (VOUT(NOM) + 0.5 V) to 3.3 V, IOUT = 1 mA | 5 | |||
| Load regulation | 0.002 | %/mA | IOUT = 1 mA to 300 mA | 5 | |||
| Quiescent current | IQ | 12 | 25 | µA | VEN = 1 V, IOUT = 0 mA | 5 | |
| Quiescent current at full load | IQ | 230 | 350 | µA | VEN = 1 V, IOUT = 300 mA | 5 | |
| Quiescent current in shutdown | IQ(SD) | 0.02 | 2 | µA | VEN = 0.3 V, -40°C <= TJ <= 85°C | 5 | |
| Ground current | IG | 15 | µA | IOUT = 0 mA (VOUT = 2.3 V) | 5 | ||
| Output noise voltage | eN | 12 | µVRMS | BW = 10 Hz to 100 kHz, IOUT = 300 mA | 6 | ||
| Thermal shutdown | TSD | 160 | °C | TJ rising until output is OFF | 6 | ||
| Thermal hysteresis | 15 | °C | TJ falling from shutdown | 6 | |||
| Power supply rejection ratio at 100 Hz | PSRR | 80 | dB | f = 100 Hz, IOUT = 20 mA, VOUT >= 1 V | 6 | ||
| Power supply rejection ratio at 1 kHz | PSRR | 75 | dB | f = 1 kHz, IOUT = 20 mA, VOUT >= 1 V | 6 | ||
| Power supply rejection ratio at 10 kHz | PSRR | 65 | dB | f = 10 kHz, IOUT = 20 mA, VOUT >= 1 V | 6 | ||
| Power supply rejection ratio at 100 kHz | PSRR | 40 | dB | f = 100 kHz, IOUT = 20 mA, VOUT >= 1 V | 6 | ||
| Power supply rejection ratio at 2 MHz | PSRR | 25 | dB | f = 2 MHz, IOUT = 20 mA, VOUT >= 1 V | 6 | ||
| Overshoot on start-up | 5 | % | 6 | ||||
| Turnon time | tON | 80 | 200 | µs | From VEN > VIH to VOUT = 95% of VOUT(NOM) | 6 | |
| Output discharge pulldown resistance | RAD | 160 | Ω | VEN = 0 V, VIN = 2.3 V | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 79.2 | °C/W | WSON (DRV), High-K PCB | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 110.2 | °C/W | WSON (DRV) | 5 | ||
| Junction-to-board thermal resistance | RθJB | 48.7 | °C/W | WSON (DRV) | 5 | ||
| Junction-to-top characterization parameter | ψJT | 5.2 | °C/W | WSON (DRV) | 5 | ||
| Junction-to-board characterization parameter | ψJB | 49.1 | °C/W | WSON (DRV) | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 18.1 | °C/W | WSON (DRV) | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | GND pin using as wide and as short of a copper trace as is practical. | 18 |
CAD (KiCad official)
- Symbol:
LP5910-1.8DRVT - Footprint:
Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm - 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
lp5910-1-8drvt-etched.step/lp5910-1-8drvt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lp5910-1-8drvt.step/lp5910-1-8drvt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
43abbb31e587c156, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).