component

LP5868RKPR

Public Made by Adom

by adom

TEXAS INSTRUMENTS Global Sourcing Parts, VQFN-40(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentglobal sourcing partslp5868rkprfactory-2.0.0extractor-text

Verified LP5868RKPR

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LP5868RKPR · VQFN-40(5x5) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 56-page datasheet
  • ✓distributor: lcsc C3189475, digikey 296-LP5868RKPRTR-ND, mouser 595-LP5868RKPR
  • ✓family: QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-tw2qbwo5/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lp5868rkpr.kicad_sym✓ lp5868rkpr.kicad_mod✓ lp5868rkpr.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
lp5868rkpr / README.md
History Download
Ray Publish 0.1.0 b1aaba3 4d ago

LP5868RKPR

TEXAS INSTRUMENTS · Global Sourcing Parts · VQFN-40(5x5)

LP5868RKPR from TEXAS INSTRUMENTS, in a VQFN-40(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS0 output Current sink 0; must be left floating if not used.
2 CS1 output Current sink 1; must be left floating if not used.
3 CS2 output Current sink 2; must be left floating if not used.
4 CS3 output Current sink 3; must be left floating if not used.
5 CS4 output Current sink 4; must be left floating if not used.
6 CS5 output Current sink 5; must be left floating if not used.
7 CS6 output Current sink 6; must be left floating if not used.
8 CS7 output Current sink 7; must be left floating if not used.
9 CS8 output Current sink 8; must be left floating if not used.
10 SW0 output High-side PMOS switch output for scan line 0; must be left floating if not used.
11 SW1 output High-side PMOS switch output for scan line 1; must be left floating if not used.
12 SW2 output High-side PMOS switch output for scan line 2; must be left floating if not used.
13 SW3 output High-side PMOS switch output for scan line 3; must be left floating if not used.
14 SW4 output High-side PMOS switch output for scan line 4; must be left floating if not used.
15 SW5 output High-side PMOS switch output for scan line 5; must be left floating if not used.
16 VLED power_in Power input for high-side switches; supply range 2.7 V to 5.5 V.
17 SW6 output High-side PMOS switch output for scan line 6; must be left floating if not used.
18 SW7 output High-side PMOS switch output for scan line 7; must be left floating if not used.
19 NC unconnected No internal connection.
20 NC unconnected No internal connection.
21 NC unconnected No internal connection.
22 CS9 output Current sink 9; must be left floating if not used.
23 CS10 output Current sink 10; must be left floating if not used.
24 CS11 output Current sink 11; must be left floating if not used.
25 CS12 output Current sink 12; must be left floating if not used.
26 CS13 output Current sink 13; must be left floating if not used.
27 CS14 output Current sink 14; must be left floating if not used.
28 CS15 output Current sink 15; must be left floating if not used.
29 CS16 output Current sink 16; must be left floating if not used.
30 CS17 output Current sink 17; must be left floating if not used.
31 AGND power_in Analog ground; must be connected to the exposed thermal pad and common ground plane.
32 VCAP power_out Internal LDO output; a 1-µF capacitor must be connected between this pin and GND, placed as close to the device as possible.
33 IFS input Interface type select: I2C when low, SPI when high; a resistor must be connected between VIO and this pin.
34 VSYNC input External synchronize signal for display mode 2 and mode 3.
35 SCL_SCLK input I2C clock input or SPI clock input; pull up to VIO when configured as I2C.
36 SDA_MOSI bidirectional I2C data input/output or SPI leader output/follower input; pull up to VIO when configured as I2C.
37 ADDR0_MISO bidirectional I2C address select 0 or SPI leader input/follower output.
38 ADDR1_SS input I2C address select 1 or SPI follower select.
39 VIO_EN power_in Power supply for digital circuits and chip enable; a 1-nF capacitor must be connected between this pin and GND, placed as close to the device as possible.
40 VCC power_in Power supply for device; a 1-µF capacitor must be connected between this pin and GND, placed as close to the device as possible.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer TEXAS INSTRUMENTS
Package VQFN-40(5x5)
Category Global Sourcing Parts
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage on VCC / VLED / VIO / EN / CS / SW / SDA / SCL / SCLK / MOSI / MISO / SS / ADDR0 / ADDR1 / VSYNC / IFS -0.3 6 V 6
Voltage on VCAP -0.3 2 V 6
Junction temperature TJ -55 150 °C 6
Storage temperature Tstg -65 150 °C 6
Input voltage on VCC (supply voltage) VCC 2.7 5.5 V 6
Input voltage on VLED (LED supply voltage) VLED 2.7 5.5 V 6
Input voltage on VIO_EN VIO_EN 1.65 5.5 V 6
Operating ambient temperature TA -40 85 °C 6
Constant current sink output range (CS0, CS17) ICS 0.1 40 mA 2.7 <= VCC < 3.3V, PWM = 100% 7
Constant current sink output range (CS0, CS17) ICS 0.1 50 mA VCC >= 3.3V PWM = 100% 7
Device to device current error IERR_DD -7 7 % All channels ON. Current set to 0.1 mA. MC = 0 CC = 42 DC = 25 PWM = 100% 7
Device to device current error IERR_DD -5 5 % All channels ON. Current set to 1 mA. MC = 2 CC = 127 DC = 25 PWM = 100% 7
Device to device current error IERR_DD -3.5 3.5 % All channels ON. Current set to 10 mA. MC = 2 CC = 127 DC = 255 PWM = 100% 7
Device to device current error IERR_DD -3 3 % All channels ON. Current set to 50 mA. MC = 7 CC = 127 DC = 255 PWM = 100% 7
Channel to channel current error IERR_CC -5.5 5.5 % All channels ON. Current set to 0.1 mA. MC = 0 CC = 42 DC = 25 PWM = 100% 7
Channel to channel current error IERR_CC -5 5 % All channels ON. Current set to 1 mA. MC = 2 CC = 127 DC = 25 PWM = 100% 7
Channel to channel current error IERR_CC -4 4 % All channels ON. Current set to 10 mA. MC = 2 CC = 127 DC = 255 PWM = 100% 7
Channel to channel current error IERR_CC -3.5 3.5 % All channels ON. Current set to 25 mA. MC = 7 CC = 64 DC = 255 PWM = 100% 7
Channel to channel current error IERR_CC -3 3 % All channels ON. Current set to 50 mA. MC = 7 CC = 127 DC = 255 PWM = 100% 7
VVIO VIO supply voltage VVIO 1.65 5.5 V 7
Shutdown supply current ISHUTDOWN 0.1 1 µA VEN = 0V, CHIP_EN = 0 (bit), measure the total current from VCC and VLED 7
Standby supply current ISTANDBY 5.5 10 µA VEN = 3.3V, CHIP_EN = 0 (bit), measure the total current from VCC and VLED 7
Active mode supply current INORMAL 4.3 6 mA VEN = 3.3V, CHIP_EN = 1 (bit), all channels IOUT = 5 mA (MC = 1, CC = 127, DC = 256), measure the current from VCC 7
Leakage current (CS0, CS17) ILKG 0.1 1 µA channels off, up_deghost = 0, VCS=5V 7
High-side PMOS ON resistance RSW 450 550 mΩ VLED = 2.7 V, ISW = 200 mA 8
High-side PMOS ON resistance RSW 380 500 mΩ VLED = 3.8 V, ISW = 200mA 8
High-side PMOS ON resistance RSW 310 450 mΩ VLED = 5 V, ISW = 200 mA 8
Output saturation voltage VSAT 0.45 V IOUT = 50mA, decreasing output voltage, when the LED current has dropped 5% 8
Output saturation voltage VSAT 0.4 V IOUT = 30mA, decreasing output voltage, when the LED current has dropped 5% 8
Output saturation voltage VSAT 0.35 V IOUT = 10mA, decreasing output voltage, when the LED current has dropped 5% 8
Low-level input voltage of EN VEN_IL 0.4 V 8
High-level input voltage of EN VEN_IH 1.4 V When VCAP powered up 8
Input current, SDA, SCL, SCLK, MOSI, SS, ADDRx ILOGIC_I -1 1 µA 8
Low-level output voltage, SDA, MISO VLOGIC_OL 0.4 V IPULLUP = 3 mA 8
Undervoltage restart VUVR 2.5 V VCC rising, Test mode 7
Undervoltage shutdown VUVF 1.9 V VCC falling, Test mode 7
Undervoltage shutdown hysteresis VUV_HYS 0.3 V 7
Internal LDO output VCAP 1.78 V VCC = 2.7V to 5.5V 7
VIO supply current IVIO 5 µA Interface idle 7
LED PWM frequency fPWM 62.5 KHz PWM_Fre = 1, PWM = 100% 7
LED PWM frequency fPWM 125 KHz PWM_Fre = 0, PWM = 100% 7
Thershold for channel open detection VLOD_TH 0.25 V 8
Thermal-shutdown junction temperature TTSD 150 °C 8
Thermal shutdown temperature hysteresis THYS 15 °C 8
Junction-to-ambient thermal resistance RθJA 31.4 °C/W 6
Junction-to-case (top) thermal resistance RθJC(top) 22.9 °C/W 6
Junction-to-board thermal resistance RθJB 12 °C/W 6
Junction-to-top characterization parameter ΨJT 0.3 °C/W 6
Junction-to-board characterization parameter ΨJB 12 °C/W 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 3.5 °C/W 6
Internal oscillator frequency fOSC 31.2 MHz 8
Device to device oscillator frequency error fOSC_ERR -3 3 % 8
Wait time from UVLO disactive to device NORMAL tPOR_H 500 µs 8
Wait time from setting Chip_EN (Register) =1 to device NORMAL tCHIP_EN 100 µs 8
LED output rise time tRISE 10 ns 8
LED output fall time tFALL 15 ns 8
The minimum high-level pulse width of VSYNC tVSYNC_H 200 µs 8
SPI Clock frequency fSCLK 12 MHz 9

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper possible. GND plane connections to CVLED and GND pins must be on the TOP layer copper with multiple vias 47

CAD (KiCad official)

  • Symbol: LP5868RKPR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: VQFN-40(5x5) (KiCad packages3D, STEP)
  • 3D model files: lp5868rkpr-etched.step / lp5868rkpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp5868rkpr.step / lp5868rkpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TEXAS INSTRUMENTS datasheet (56 pp, sha256 1af4cf028d736334, retrieved 2026-11-02, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF