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Ray Publish 0.1.0 6e60028 11d ago

LP5301QVF

LOWPOWER · Battery Management ICs · DFN-8-EP(2x2)

LP5301QVF from LOWPOWER, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Input pin; a 1uF low ESR ceramic capacitor or larger must be connected as close as possible to this pin, with a 50V capacitor recommended or as the application requires.
2 GND power_in Ground pin.
3 NC unconnected No connect; this pin must be left floating without connecting to GND or a high voltage.
4 NC unconnected No connect; this pin must be left floating without connecting to GND or a high voltage.
5 EN input Chip enable pin, active low; VEN(L) maximum is 0.4 V and VEN(H) minimum is 1.4 V.
6 NC unconnected No connect; this pin must be left floating without connecting to GND or a high voltage.
7 ISET passive Current program pin; connect a resistor to ground to set the OCP threshold (RSET options 51K, 82K, 150K or NC).
8 VOUT power_out Output pin that connects to VIN through the internal MOSFET, which is switched off on OVP or OCP events.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer LOWPOWER
Package DFN-8-EP(2x2)
Category Power Management ICs
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage to GND 36 V 3
Output Voltage to GND 6.5 V 3
Other Pin to GND 6 V 3
Maximum Junction Temperature 150 °C 3
Operating Ambient Temperature Range (TA) TA -40 85 °C 3
HBM (Human Body Model) ESD 2 KV Human Body Model 3
MM (Machine Model) ESD 200 V Machine Mode 3
Thermal Resistance (DFN-8, θJA) θJA 46 ℃/W DFN-8 3
Maximum Power Dissipation (DFN-8, PD) PD 1.5 W DFN-8, TA=25°C 3
VIN Input Voltage VIN 3.5 36 V 4
Enable Threshold Low VEN(L) 0.4 V Chip enable 4
Enable Threshold High VEN(H) 1.4 5 V Chip shutdown 4
Under voltage lock out threshold UVLO 2.6 2.8 3 V VIN increasing from 0~5V 4
Under voltage lock out hysteresis VHYS-UVLO 500 mV VIN decreasing from 5~0V 4
OVP threshold VOVP 5.8 6.1 6.4 V VIN increasing from 5~7V 4
OVP hysteresis VHYS-OVP 300 mV VIN decreasing from 7~5V 4
IOCP Limit Current IOCPLIMIT 2.1 2.5 A RSET=NC 4
Input quiescent current IQ 110 μA EN=LOW, IOUT=0A 4
Input shutdown current ISD 1 μA EN=HIGH, IOUT=0A 4
IN-to-OUT ON resistance RON 130 mΩ IOUT=1A 4
Output discharge resistance RDISCHARGE 4.3 kΩ 4
Output power-on time TON 9 ms EN=LOW, VIN=0->5V to output ON 4
Turn on through EN TON 9 ms EN=HIGH->LOW to output ON 4
OVP active time TOVP 1 μs VIN=5→10V 4
OVP recovery time TON(OVP) 9 ms VIN=10→5V to output ON 4
OCP threshold IOCP 1.9 A RSET=51K 4
OCP threshold IOCP 1.3 A RSET=82K 4
OCP threshold IOCP 0.85 A RSET=150K 4
OCP active time TOCP 30 ms 4
ISET Voltage VISET 0.8 V 4
OCP recovery time TON(OCP) 1 s 4
OTP threshold TOTP 150 ℃ 4
OTP hysteresis TOTP_HYS 20 ℃ 4

CAD (KiCad official)

  • Symbol: LP5301QVF
  • Footprint: Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm
  • 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: lp5301qvf-etched.step / lp5301qvf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp5301qvf.step / lp5301qvf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LOWPOWER datasheet (8 pp, sha256 61dd519d2eabc92b, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF