component
LP4565T1G
Public Made by Adomby adom
LRC MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LP4565T1G
LRC · MOSFETs · SO-8
LP4565T1G from LRC, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied internally with pins 2 and 3 in the pin diagram; VDSS is -60 V and continuous source current (diode conduction) is -1.6 A. |
| 2 | S | passive | Source of the P-channel MOSFET, tied internally with pins 1 and 3 in the pin diagram; VDSS is -60 V and continuous source current (diode conduction) is -1.6 A. |
| 3 | S | passive | Source of the P-channel MOSFET, tied internally with pins 1 and 2 in the pin diagram; VDSS is -60 V and continuous source current (diode conduction) is -1.6 A. |
| 4 | G | input | Gate of the P-channel MOSFET; gate-to-source voltage limit is ±20 V with threshold VGS(th) of -1 V at ID = -250 uA. |
| 5 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 6, 7 and 8; VDSS is -60 V and continuous drain current is -7 A at TA = 25°C. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 7 and 8; VDSS is -60 V and continuous drain current is -7 A at TA = 25°C. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 6 and 8; VDSS is -60 V and continuous drain current is -7 A at TA = 25°C. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 6 and 7; VDSS is -60 V and continuous drain current is -7 A at TA = 25°C. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SO-8 |
| Category | Transistors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-to-Source Voltage | VDSS | -60 | V | 1 | |||
| Gate-to-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Continuous Drain Current, TA=25°C | ID | -7 | A | TA = 25°C, surface mounted on 1in x 1in FR4 board, t≤10 s / steady state per Note 1 | 1 | ||
| Continuous Drain Current, TA=70°C | ID | -5 | A | TA = 70°C, Note 1 | 1 | ||
| Pulsed Drain Current | IDM | -20 | A | Pulse width limited by maximum junction temperature (Note 2) | 1 | ||
| Continuous Source Current (Diode Conduction) | IS | -1.6 | A | Note 1 | 1 | ||
| Power Dissipation, TA=25°C | PD | 2.9 | W | TA = 25°C, Note 1 | 1 | ||
| Power Dissipation, TA=70°C | PD | 1.8 | W | TA = 70°C, Note 1 | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, TSTG | -55 | 150 | ºC | 1 | ||
| Maximum Junction-to-Ambient Thermal Resistance | RθJA | 45 | ºC/W | t ≤ 10 s, Note 1 | 1 | ||
| Maximum Junction-to-Ambient Thermal Resistance | RθJA | 95 | ºC/W | Steady state, Note 1 | 1 | ||
| Gate-Source Threshold Voltage | VGS(th) | -1 | V | VDS = VGS, ID = -250 uA | 2 | ||
| Gate-Body Leakage | IGSS | -10 | 10 | uA | VDS = 0 V, VGS = ±20 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | -1 | uA | VDS = -48 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current, TJ = 55°C | IDSS | -10 | uA | VDS = -48 V, VGS = 0 V, TJ = 55°C | 2 | ||
| On-State Drain Current | ID(on) | -7.5 | A | VDS = -5 V, VGS = -10 V | 2 | ||
| Drain-Source On-Resistance, VGS=-10 V | rDS(on) | 82 | mΩ | VGS = -10 V, ID = -4 A | 2 | ||
| Drain-Source On-Resistance, VGS=-4.5 V | rDS(on) | 100 | mΩ | VGS = -4.5 V, ID = -3.2 A | 2 | ||
| Diode Forward Voltage | VSD | -0.83 | V | IS = -2.1 A, VGS = 0 V | 2 |
CAD (KiCad official)
- Symbol:
LP4565T1G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
lp4565t1g-etched.step/lp4565t1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lp4565t1g.step/lp4565t1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LRC datasheet (3 pp, sha256
00873b0a8b567a53, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LP4565T1G
**LRC** · MOSFETs · SO-8
LP4565T1G from LRC, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied internally with pins 2 and 3 in the pin diagram; VDSS is -60 V and continuous source current (diode conduction) is -1.6 A. |
| 2 | S | passive | Source of the P-channel MOSFET, tied internally with pins 1 and 3 in the pin diagram; VDSS is -60 V and continuous source current (diode conduction) is -1.6 A. |
| 3 | S | passive | Source of the P-channel MOSFET, tied internally with pins 1 and 2 in the pin diagram; VDSS is -60 V and continuous source current (diode conduction) is -1.6 A. |
| 4 | G | input | Gate of the P-channel MOSFET; gate-to-source voltage limit is ±20 V with threshold VGS(th) of -1 V at ID = -250 uA. |
| 5 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 6, 7 and 8; VDSS is -60 V and continuous drain current is -7 A at TA = 25°C. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 7 and 8; VDSS is -60 V and continuous drain current is -7 A at TA = 25°C. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 6 and 8; VDSS is -60 V and continuous drain current is -7 A at TA = 25°C. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 6 and 7; VDSS is -60 V and continuous drain current is -7 A at TA = 25°C. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SO-8 |
| Category | Transistors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-to-Source Voltage | VDSS | -60 | | | V | | 1 |
| Gate-to-Source Voltage | VGS | -20 | | 20 | V | | 1 |
| Continuous Drain Current, TA=25°C | ID | -7 | | | A | TA = 25°C, surface mounted on 1in x 1in FR4 board, t≤10 s / steady state per Note 1 | 1 |
| Continuous Drain Current, TA=70°C | ID | -5 | | | A | TA = 70°C, Note 1 | 1 |
| Pulsed Drain Current | IDM | -20 | | | A | Pulse width limited by maximum junction temperature (Note 2) | 1 |
| Continuous Source Current (Diode Conduction) | IS | -1.6 | | | A | Note 1 | 1 |
| Power Dissipation, TA=25°C | PD | | | 2.9 | W | TA = 25°C, Note 1 | 1 |
| Power Dissipation, TA=70°C | PD | | | 1.8 | W | TA = 70°C, Note 1 | 1 |
| Operating Junction and Storage Temperature Range | TJ, TSTG | -55 | | 150 | ºC | | 1 |
| Maximum Junction-to-Ambient Thermal Resistance | RθJA | | | 45 | ºC/W | t ≤ 10 s, Note 1 | 1 |
| Maximum Junction-to-Ambient Thermal Resistance | RθJA | | | 95 | ºC/W | Steady state, Note 1 | 1 |
| Gate-Source Threshold Voltage | VGS(th) | | | -1 | V | VDS = VGS, ID = -250 uA | 2 |
| Gate-Body Leakage | IGSS | -10 | | 10 | uA | VDS = 0 V, VGS = ±20 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | -1 | uA | VDS = -48 V, VGS = 0 V | 2 |
| Zero Gate Voltage Drain Current, TJ = 55°C | IDSS | | | -10 | uA | VDS = -48 V, VGS = 0 V, TJ = 55°C | 2 |
| On-State Drain Current | ID(on) | -7.5 | | | A | VDS = -5 V, VGS = -10 V | 2 |
| Drain-Source On-Resistance, VGS=-10 V | rDS(on) | | | 82 | mΩ | VGS = -10 V, ID = -4 A | 2 |
| Drain-Source On-Resistance, VGS=-4.5 V | rDS(on) | | | 100 | mΩ | VGS = -4.5 V, ID = -3.2 A | 2 |
| Diode Forward Voltage | VSD | | | -0.83 | V | IS = -2.1 A, VGS = 0 V | 2 |
## CAD (KiCad official)
- Symbol: `LP4565T1G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `lp4565t1g-etched.step` / `lp4565t1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lp4565t1g.step` / `lp4565t1g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [LRC datasheet](docs/lp4565t1g-datasheet.pdf) (3 pp, sha256 `00873b0a8b567a53`, retrieved 2026-10-22, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lp4565t1g-datasheet.pdf)