# LP4069TQVF

**LOWPOWER** · Battery Management · DFN-8-EP(2x2)

LP4069TQVF from LOWPOWER, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input power source connected to a wall adapter; the input is rated -0.3V to 28V to GND, the charger is automatically disabled above the 7V input OVP threshold, and the UVLO threshold is 3.5V (rising). |
| 2 | FULL | output | Open-drain charge-complete status output: it is pulled low by an internal N-MOS when the charge cycle is completed and is high-impedance while charging, so it needs an external pull-up resistor; other pins are rated -0.3V to 6.5V to GND. |
| 3 | CHRG | output | Open-drain charge status output: it is pulled low by an internal N-MOS (about 5mA strong pull-down, VSTAT 0.5V max at 5mA) while charging and goes high-impedance when charge is finished, so it needs an external pull-up resistor. |
| 4 | EN | input | Active-low charge enable input, with logic-low threshold VEN_ON of 0.4V max and logic-high threshold VEN_OFF of 1.4V min. |
| 5 | GND | power_in | System ground connection, which is the reference for all pin voltage ratings and the TS and ISET networks. |
| 6 | TS | input | Battery temperature sense input that stops charging when the thermistor voltage is out of range (VTS_H at 30% of VIN, VTS_L at 60% of VIN, 90mV hysteresis); connect to GND to disable this function, or hold it below VTS_DIS (0.2V). |
| 7 | ISET | passive | Charge current program pin: a 1% resistor RISET to GND sets IBAT (for example 17k gives 100mA and 3.4k gives 500mA typical), with VISET regulated at 1V in current mode. |
| 8 | BAT | power_out | Connection to the single-cell Li-ion or Li-polymer battery, with a fixed float voltage of 4.2V for LP4069TQVF (4.35V for the -435 variant); a 10µF tantalum capacitor is typically needed for stability when no battery is attached, and BAT is rated -5V to 15V. |
| 9 | PAD | passive | Exposed thermal pad used to strengthen heat dissipation, which the datasheet says is usually connected to GND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | LOWPOWER |
| Package | DFN-8-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 9 |

## CAD (KiCad official)

- Symbol: `LP4069TQVF`
- Footprint: `Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm`
- 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files: `lp4069tqvf-etched.step` / `lp4069tqvf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lp4069tqvf.step` / `lp4069tqvf.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [LOWPOWER datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588920121829679104) (9 pp, sha256 `e0c3618fdb351c0a`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lp4069tqvf-datasheet.pdf)