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LP3985IM5-2.5

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)lp3985im5-2.5factory-2.0.0extractor-text

Verified LP3985IM5-2.5

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 5 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LP3985IM5-2.5 · SOT-23-5 · 5 pins
  • ✓copper: 5 copper pads, none touching another net
  • ✓datasheet: all 5 pin names found in the 34-page datasheet
  • ✓distributor: lcsc C201609, digikey 296-LP3985IM5-2.5TR-ND, mouser 926-LP3985IM5-25
  • ✓family: SOT-23-5
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-f7ulo6i6/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 5 pins = 5 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 5 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lp3985im5-2-5.kicad_sym✓ lp3985im5-2-5.kicad_mod✓ lp3985im5-2-5.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers lp3985im5-2-5: viewers · Ray 1d ago
lp3985im5-2-5-etched.glb Publish 0.1.0 · Ray 1d ago
lp3985im5-2-5-etched.step lp3985im5-2-5: factory component page (tier=mfr) · Ray 1d ago
lp3985im5-2-5-hero.glb lp3985im5-2-5: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
lp3985im5-2-5-hero.overlay.json Publish 0.1.0 · Ray 1d ago
lp3985im5-2-5.glb Publish 0.1.0 · Ray 1d ago
lp3985im5-2-5.kicad_mod Publish 0.1.0 · Ray 1d ago
lp3985im5-2-5.kicad_sym Publish 0.1.0 · Ray 1d ago
lp3985im5-2-5.lbr Publish 0.1.0 · Ray 1d ago
lp3985im5-2-5.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 5 pins · Ray 1d ago

LP3985IM5-2.5

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

LP3985IM5-2.5 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN input Input voltage of the LDO, specified at 2.5 V to 6 V in recommended operating conditions with an absolute maximum of 6.5 V.
2 GND power_in Common ground, to which all voltages in the datasheet are referenced.
3 EN input Enable input logic, enable high, with an ON/OFF input voltage range of 0 V to VIN.
4 BYPASS bidirectional Optional bypass capacitor connection for noise reduction.
5 OUT output Output voltage of the LDO, rated for an output current of 150 mA.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage tolerance (TA = 25°C) VOUT -2 2 % IOUT = 1 mA; TA = 25°C only 5
Output voltage tolerance (over temperature) VOUT -3 3 % IOUT = 1 mA 5
Line regulation error (all other options) ΔVOUT -0.1 0.1 %/V VIN = (VOUT(nom) + 0.5 V) to 6 V 5
Load regulation error (LP3985IM5 SOT23-5) 0.0025 0.005 %/mA IOUT = 1 mA to 150 mA 5
Quiescent current, IOUT = 0 mA (all other options) IQ 85 150 µA VEN = 1.4 V, IOUT = 0 mA 5
Quiescent current, IOUT = 0 to 150 mA (all other options) IQ 140 200 µA VEN = 1.4 V, IOUT = 0 to 150 mA 5
Shutdown current IQ 0.003 1.5 µA VEN = 0.4 V 5
Dropout voltage 0.4 2 mV IOUT = 1 mA 5
Dropout voltage 20 35 mV IOUT = 50 mA 5
Dropout voltage 45 70 mV IOUT = 100 mA 5
Dropout voltage 60 100 mV IOUT = 150 mA 5
Peak output current IOUT(PK) 300 550 mA VOUT ≥ VOUT(nom), 5% 5
Maximum input current at EN IEN -1 1 nA VEN = 0.4 V and VIN = 6 V 5
Maximum low-level input voltage at EN VIL 0.4 V VIN = 2.5 V to 6 V 5
Minimum high-level input voltage at EN VIH 1.4 V VIN = 2.5 V to 6 V 5
Output AC line regulation 1.5 mVP-P VIN = VOUT(nom) + 1 V, IOUT = 150 mA (Figure 1) 5
Power supply rejection ratio PSRR 50 dB f = 1 kHz, VIN = VOUT(nom) + 0.2 V, IOUT = 50 mA (Figure 2) 5
Power supply rejection ratio PSRR 40 dB f = 10 kHz, VIN = VOUT(nom) + 0.2 V, IOUT = 50 mA (Figure 2) 5
Turnon time TON 200 µs CBYPASS = 0.01 µF 5
Output noise voltage en 30 µVRMS BW = 10 Hz to 100 kHz, COUT = 1 µF 5
Output noise density en 230 nV/√Hz CBP = 0 5
Short circuit current limit ISC 600 mA Output grounded, steady state 5
Thermal shutdown temperature TSD 160 °C 5
Thermal shutdown hysteresis 20 °C 5
Supply input voltage (absolute maximum, IN and EN) VIN -0.3 6.5 V IN, EN pins 4
Output voltage (absolute maximum) VOUT -0.3 V OUT pin, max (VIN + 0.3) < 6.5 V 4
Junction temperature (absolute maximum) TJ 150 °C 4
Lead temperature 235 °C 4
Pad temperature 235 °C 4
Maximum power dissipation (SOT-23) PD 364 mW SOT-23(5) package 4
Storage temperature Tstg -65 150 °C 4
ESD, human-body model V(ESD) -2000 2000 V HBM, per ANSI/ESDA/JEDEC JS-001 4
Supply input voltage (recommended) VIN 2.5 6 V 4
ON/OFF input voltage (recommended) VEN 0 V max VIN 4
Output current (recommended) IOUT 150 mA 4
Operating junction temperature (recommended) TJ -40 125 °C 4
Junction-to-ambient thermal resistance (SOT-23) RθJA 220 °C/W SOT-23 (DBV), 5 pins 4
Junction-to-case (top) thermal resistance (SOT-23) RθJC(top) 79.8 °C/W SOT-23 (DBV), 5 pins 4
Junction-to-board thermal resistance (SOT-23) RθJB 31.6 °C/W SOT-23 (DBV), 5 pins 4
Junction-to-top characterization parameter (SOT-23) ψJT 3.1 °C/W SOT-23 (DBV), 5 pins 4
Junction-to-board characterization parameter (SOT-23) ψJB 31.1 °C/W SOT-23 (DBV), 5 pins 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is stron 19

CAD (KiCad official)

  • Symbol: LP3985IM5-2.5
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: lp3985im5-2-5-etched.step / lp3985im5-2-5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp3985im5-2-5.step / lp3985im5-2-5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 ec4787d8991ef2e7, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF