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LP3982H-28B5F
Public Made by Adomby adom
LOWPOWER Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownLP3982H-28B5F
LOWPOWER · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
LP3982H-28B5F from LOWPOWER, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Supply input pin that must be closely decoupled to GND with a 1μF or greater ceramic capacitor placed as close to the pin as possible; input voltage range is 2.2V to 5.5V. |
| 2 | GND | power_in | Ground pin. |
| 3 | EN | input | Active-high enable pin: driving EN over 1V turns on the regulator and driving EN below 0.4V puts it into shutdown mode. |
| 4 | NC | unconnected | No connection. |
| 5 | VOUT | power_out | Regulated output pin that must be bypassed with a 1μF or greater ceramic capacitor to ground, placed as close to the pin as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LOWPOWER |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Operation Range | VIN | 2.2 | 5.5 | V | 5 | ||
| Inrush Current | IInrush | 400 | mA | COUT=10μF | 5 | ||
| DC Supply Quiescent Current | IQ | 58 | μA | IOUT=0mA | 5 | ||
| Shutdown Current | ISD | 0.6 | μA | VEN=0V | 5 | ||
| Output Voltage Accuracy (2.8V variant) | VOUT | 2.772 | 2.8 | 2.828 | V | IOUT=1mA | 5 |
| Output Voltage Line Regulation | 0.01 | %/V | VIN=VOUT+0.5V~5.5V IOUT=1mA | 5 | |||
| Output Voltage Load Regulation | ΔVLOAD | 36 | 70 | mV | IOUT from 1mA to 600mA | 5 | |
| VOUT Temperature Coefficient | TCVOUT | 0.01 | %/℃ | IOUT=1mA | 5 | ||
| Max Load Current | IOUT_MAX | 600 | mA | VEN=VIN | 5 | ||
| Load Current Limit | ILIMIT | 800 | 1100 | mA | VEN=VIN | 5 | |
| Short Current | ISHORT | 195 | mA | VEN=VIN, VOUT short to GND | 5 | ||
| Power Supply Rejection Ratio at 100Hz | PSRR | 80 | dB | VIN=(VOUT+1V)DC+0.2VP-P, IOUT=20mA, VOUT=2.8V, f=100Hz | 5 | ||
| Power Supply Rejection Ratio at 1kHz | PSRR | 75 | dB | VIN=(VOUT+1V)DC+0.2VP-P, IOUT=20mA, VOUT=2.8V, f=1kHz | 5 | ||
| Power Supply Rejection Ratio at 10kHz | PSRR | 60 | dB | VIN=(VOUT+1V)DC+0.2VP-P, IOUT=20mA, VOUT=2.8V, f=10kHz | 5 | ||
| Power Supply Rejection Ratio at 100kHz | PSRR | 50 | dB | VIN=(VOUT+1V)DC+0.2VP-P, IOUT=20mA, VOUT=2.8V, f=100kHz | 5 | ||
| Output Noise Voltage (2.8V variant) | eN | 42 | μVRMS | 10Hz~100kHz, IOUT=20mA, VOUT=2.8V | 5 | ||
| Thermal Shutdown Threshold | TSD | 160 | ℃ | 6 | |||
| Thermal Shutdown Hysteresis | ΔTSD | 20 | ℃ | 6 | |||
| VOUT Rise Time | trise | 30 | μs | IOUT=0mA | 6 | ||
| Auto-discharge On-Resistance | RDISC | 850 | Ω | 6 | |||
| EN Logic High Voltage | VENH | 1 | V | 6 | |||
| EN Logic Low Voltage | VENL | 0.4 | V | 6 | |||
| EN Input Current | IEN | 120 | nA | VEN=0 to 5.5V | 6 | ||
| VIN Pin to GND | -0.3 | 6.5 | V | 4 | |||
| VOUT, EN Pin to GND | -0.3 | V | 4 | ||||
| Maximum Junction Temperature | TJ | 150 | ℃ | 4 | |||
| Operating Ambient Temperature Range | TA | -40 | 85 | ℃ | 4 | ||
| Maximum Soldering Temperature | 260 | ℃ | at leads, 10 sec | 4 | |||
| ESD Human Body Model | 4 | kV | HBM | 4 | |||
| ESD Charged Device Model | 1 | kV | CDM | 4 | |||
| Input Voltage (recommended) | 2.2 | 5.5 | V | 4 | |||
| Operating Junction Temperature Range | TJ | -40 | 150 | ℃ | 4 | ||
| Ambient Temperature Range (recommended) | TA | -40 | 85 | ℃ | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | practically possible to the respective LDO pins. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close to each other as possible with a wide and compon | 12 |
CAD (KiCad official)
- Symbol:
LP3982H-28B5F - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
lp3982h-28b5f-etched.step/lp3982h-28b5f-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lp3982h-28b5f.step/lp3982h-28b5f.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LOWPOWER datasheet (18 pp, sha256
fdcbfba8996262fb, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).