# LP3906SQ-JXXI

**Texas Instruments** · Battery Management · WQFN-24-EP(4x5)

LP3906SQ-JXXI from Texas Instruments, in a WQFN-24-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN2 | power_in | Power in from either DC source or Battery to Buck 2. |
| 2 | SW2 | output | Buck2 switcher output pin. |
| 3 | GND_SW2 | power_in | Buck2 NMOS Power Ground. |
| 4 | GND_C | power_in | Non switching core ground pin. |
| 5 | GND_SW1 | power_in | Buck1 NMOS Power Ground. |
| 6 | SW1 | output | Buck1 switcher output pin. |
| 7 | VIN1 | power_in | Power in from either DC source or Battery to buck 1. |
| 8 | SDA | bidirectional | I2C Data (Bidirectional). |
| 9 | SCL | input | I2C Clock. |
| 10 | EN_T | input | Enable for preset power on sequence. |
| 11 | FB1 | input | Buck1 input feedback terminal. |
| 12 | AVDD | power_in | Analog Power for Buck converters. |
| 13 | VINLDO1 | power_in | Power in from either DC source or Battery to input terminal of LDO1. |
| 14 | LDO1 | power_out | LDO1 Output. |
| 15 | ENLDO1 | input | LDO1 enable pin, a logic HIGH enables the LDO1. |
| 16 | ENLDO2 | input | LDO2 enable pin, a logic HIGH enables the LDO2. |
| 17 | GND_L | power_in | LDO Ground. |
| 18 | LDO2 | power_out | LDO2 Output. |
| 19 | VINLDO2 | power_in | Power in from either DC source or battery to input terminal to LDO2. |
| 20 | VinLDO12 | power_in | Analog Power for Internal Functions (VREF, BIAS, I2C, Logic). |
| 21 | FB2 | input | Buck2 input feedback terminal. |
| 22 | ENSW1 | input | Enable Pin for Buck1 switcher, a logic HIGH enables Buck1. |
| 23 | SYNC | input | Frequency Synchronization pin which allows the user to connect an external clock signal PLL to synchronize the PMIC internal oscillator. |
| 24 | ENSW2 | input | Enable Pin for Buck2 switcher, a logic HIGH enables Buck2. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-24-EP(4x5) |
| Category | Power Management (PMIC) |
| Pins | 25 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (VIN, SDA, SCL) | VIN, SDA, SCL | -0.3 |  | 6 | V |  | 6 |
| Power dissipation (PD_MAX) | PD_MAX |  |  | 1.43 | W | TA=85°C, TMAX=125°C | 6 |
| Junction temperature (TJ-MAX) | TJ-MAX |  |  | 150 | °C |  | 6 |
| Storage temperature range |  | -65 |  | 150 | °C |  | 6 |
| Maximum lead temperature (soldering) |  |  |  | 260 | °C |  | 6 |
| ESD rating, Human Body Model |  |  |  | 2 | kV | Human body model | 6 |
| Bucks input voltage range | VIN | 2.7 |  | 5.5 | V | Bucks | 7 |
| Junction temperature range | TJ | -40 |  | 125 | °C |  | 7 |
| Ambient temperature range | TA | -40 |  | 85 | °C |  | 7 |
| Junction-to-ambient thermal resistance | θJA |  | 28 |  | °C/W | NHZ0024B | 7 |
| LDO input operational voltage range | VIN | 1.74 |  | 5.5 | V | VINLDO1 and VINLDO2 PMOS pins | 8 |
| Output voltage accuracy (default VOUT) | VOUT | -3 |  | 3 | % | Load current = 1 mA | 8 |
| Line regulation | ΔVOUT |  |  | 0.15 | %/V | VIN = (VOUT + 0.3V) to 5.0V, Load Current = 1 mA | 8 |
| Dropout voltage | VIN, VOUT |  | 25 | 200 | mV | Load Current = 50 mA | 8 |
| ESR of output capacitor | ESR | 5 |  | 500 | mΩ |  | 8 |
| Buck output voltage accuracy (default VOUT) | VOUT | -3 |  | 3 | % | Default VOUT | 9 |
| Input low level | VIL |  |  | 0.4 | V |  | 9 |
| Input high level | VIH | 1.2 |  |  | V |  | 9 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs |  | Human Body Model (5) 2 kV (1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under | 6 |

## CAD (KiCad official)

- Symbol: `LP3906SQ-JXXI`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm`
- 3D model: WQFN-24-EP(4x5) (KiCad packages3D, STEP)
- 3D model files: `lp3906sq-jxxi-etched.step` / `lp3906sq-jxxi-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lp3906sq-jxxi.step` / `lp3906sq-jxxi.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/lp3906.pdf) (47 pp, sha256 `4315df9ad8029838`, retrieved 2026-11-06, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lp3906sq-jxxi-datasheet.pdf)