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Generated by kicad-footprint-generator · KiCad file format 20260206

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viewers	lp3881es-1-5: viewers · Ray	22d ago
lp3881es-1-5-etched.glb	lp3881es-1-5: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray	17d ago
lp3881es-1-5-etched.step	lp3881es-1-5: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray	17d ago
lp3881es-1-5-hero.glb	lp3881es-1-5: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray	17d ago
lp3881es-1-5-hero.overlay.json	lp3881es-1-5: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray	17d ago
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page.json	lp3881es-1-5: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray	17d ago
README.md	Publish 0.1.0 · Ray	22d ago

LP3881ES-1.5

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TO-263-5

LP3881ES-1.5 from Texas Instruments, in a TO-263-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	S/D	input	Active-low shutdown input that turns the regulator off when pulled low (off below 0.3V, on above 1.3V), operating range 0 to 6V, needs a 10 kΩ to 100 kΩ pull-up unless actively driven, and must be tied to VIN if unused.
2	VIN	power_in	Input voltage supplying power to the load through the N-MOS pass transistor, operating from (VOUT + VDO) to 5.5V and requiring at least 4.7 µF input capacitance.
3	GND	power_in	Ground pin, which should be returned to a clean analog ground together with the output capacitor.
4	VOUT	power_out	Regulated output (1.5V for the -1.5 option) delivering up to 0.8A, requiring at least 4.7 µF of output capacitance with ESR in the stable range, placed within 1 cm of the pin.
5	VBIAS	power_in	External bias supply that drives the gate of the N-MOS pass transistor, operating range 4.5V to 6V with an undervoltage lockout near 4V, and a 0.1 µF bias capacitor is recommended.
6	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TO-263-5
Category	Power Management (PMIC)
Pins	6

CAD (KiCad official)

Symbol: LP3881ES-1.5
Footprint: Package_TO_SOT_SMD:TO-263-5_TabPin6
3D model: TO-263-5 (KiCad packages3D, STEP)
3D model files: lp3881es-1-5-etched.step / lp3881es-1-5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp3881es-1-5.step / lp3881es-1-5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (19 pp, sha256 a4abca2fcaedc7d5, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF