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LP3475T1G

LRC · MOSFETs · SOT-23-6

LP3475T1G from LRC, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Drain passive Drain terminal of the MOSFET, rated for a drain-source voltage VDSS of -30 V.
2 Drain passive Drain terminal of the MOSFET, rated for a drain-source voltage VDSS of -30 V.
3 Gate input Gate terminal of the MOSFET, with gate-to-source voltage VGS limited to ±20 V.
4 Source passive Source terminal of the MOSFET channel; the datasheet gives no separate pin-level limit for this terminal.
5 Drain passive Drain terminal of the MOSFET, rated for a drain-source voltage VDSS of -30 V.
6 Drain passive Drain terminal of the MOSFET, rated for a drain-source voltage VDSS of -30 V.

Key specifications

Parameter Value
Manufacturer LRC
Package SOT-23-6
Category Transistors/Thyristors
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage VBRDSS -30 V VGS = 0, ID = -250μA 2
Gate Threshold Voltage VGS(th) -1 -1.4 -1.6 V VDS = VGS, ID = -250μA 2
Zero Gate Voltage Drain Current IDSS -1 μA VGS = 0, VDS = -24 V 2
Gate Leakage Current IGSS -100 100 nA VDS = 0V, VGS = ±20V 2
Static Drain-Source On-State Resistance RDS(on) 65 mΩ VGS = -10V, ID = -4A 2
Static Drain-Source On-State Resistance RDS(on) 90 mΩ VGS = -4.5V, ID = -3A 2
Forward Voltage VSD -1.5 V VGS = 0 V, IS = -1A 2
Drain-Source Voltage VDSS -30 V 1
Gate-to-Source Voltage VGS -20 20 V 1
Continuous Drain Current ID -4.5 A Ta=25℃ (Note 3) 1
Continuous Drain Current ID -3.5 A Ta=70℃ (Note 3) 1
Pulsed Drain Current IDM -18 A Ta=25℃ 1
Power Dissipation PD 1.4 W Ta=25℃ 1
Power Dissipation PD 0.9 W Ta=70℃ 1
Junction and Storage Temperature Range Tj,Tstg -55 150 ℃ 1
Thermal Resistance, Junction-to-Ambient RθJA 89 ℃/W Surface mounted on 1.5 x 1.5 FR4 board, 1 sq in pad, 2 oz Cu (Note 1) 1
Thermal Resistance, Junction-to-Ambient RθJA 160 ℃/W Surface mounted on FR4 board, minimum recommended pad size (Note 3) 1
Thermal Resistance, Junction-to-Case RθJC 30 ℃/W 1
Avalanche Current IAS 11 A 1
Avalanche Energy EAS 6.05 mJ L=0.1mH 1
Power Dissipation PD 0.8 W Note 3 1
Pulsed Drain Current IDM -11 A Note 3 1
Pulsed Drain Current ID -2.7 A Note 2, pulse width limited by maximum junction temperature 1

CAD (KiCad official)

  • Symbol: LP3475T1G
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: lp3475t1g-etched.step / lp3475t1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp3475t1g.step / lp3475t1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (7 pp, sha256 ef8238b56af463c6, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF