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LP2992IM5-1.5

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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docs lp2992im5-1-5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers lp2992im5-1-5: viewers · Ray 1mo ago
lp2992im5-1-5-etched.fit.json lp2992im5-1-5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
lp2992im5-1-5-etched.glb lp2992im5-1-5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
lp2992im5-1-5-etched.step lp2992im5-1-5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
lp2992im5-1-5.glb Publish 0.1.0 · Ray 1mo ago
lp2992im5-1-5.kicad_mod Publish 0.1.0 · Ray 1mo ago
lp2992im5-1-5.kicad_sym Publish 0.1.0 · Ray 1mo ago
lp2992im5-1-5.lbr Publish 0.1.0 · Ray 1mo ago
lp2992im5-1-5.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json lp2992im5-1-5: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md lp2992im5-1-5: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

LP2992IM5-1.5

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

LP2992IM5-1.5 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply pin. Operating range 2.5V to 16V (18V absolute max for new chip). Requires a 1µF or larger ceramic capacitor to GND placed close to the pin.
2 GND power_in Device ground reference. All bypass, input, and output capacitor return currents flow through this pin.
3 ON/OFF input Enable pin for the LDO. Driving high enables the regulator; driving low places the device into shutdown (typ 1.12µA new chip / 0.01µA legacy). Absolute max 18V; tie to VIN if enable is unused.
4 BYPASS passive Reference-noise bypass pin. Connect an external capacitor (typically 10nF) from BYPASS to GND to lower reference voltage noise and achieve the 30µVRMS output-noise specification. Internal bias node - do not drive; VBYPASS max 3V.
5 OUT power_out Regulated 1.5V output, up to 250mA load current. Requires a 2.2µF or larger ceramic output capacitor to GND (effective ≥1µF after derating). Internally current-limited and thermally protected.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • LP2992IM5-1.5
  • LP2992IM5-1.5DBV
  • LP2992IM5-1.5NGD

CAD (KiCad official)

  • Symbol: LP2992IM5-1.5
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: lp2992im5-1-5-etched.step / lp2992im5-1-5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp2992im5-1-5.step / lp2992im5-1-5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 a0b584d23febf912, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF