component
LP2992AIM5X-5.0
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLP2992AIM5X-5.0
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
LP2992AIM5X-5.0 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input supply pin, which requires a capacitor of 1µF or larger from this pin to ground. |
| 2 | GND | power_in | Ground reference pin for the regulator. |
| 3 | ON/OFF | input | Enable pin: driving it high enables the LDO and driving it low disables it, with thresholds given in the Electrical Characteristics table; tie to VIN if unused. |
| 4 | BYPASS | input | BYPASS pin for low-noise performance, where an external capacitor from BYPASS to ground reduces reference voltage noise. |
| 5 | OUT | power_out | Regulator output, which requires a capacitor of 2.2µF or larger from this pin to ground with an effective capacitance above 1µF at the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage tolerance | ΔVOUT | -1 | 1 | % | IL = 1 mA, legacy chip (A grade) | 5 | |
| Output voltage tolerance | ΔVOUT | -1.5 | 1.5 | % | 1 mA ≤ IL ≤ 50 mA, legacy chip (A grade) | 5 | |
| Output voltage tolerance | ΔVOUT | -2.5 | 2.5 | % | 1 mA ≤ IL ≤ 50 mA, -40°C ≤ TJ ≤ 125°C, legacy chip (A grade) | 5 | |
| Output voltage tolerance | ΔVOUT | -3.5 | 3.5 | % | 1 mA ≤ IL ≤ 250 mA, legacy chip (A grade) | 5 | |
| Output voltage tolerance | ΔVOUT | -4.5 | 4.5 | % | 1 mA ≤ IL ≤ 250 mA, -40°C ≤ TJ ≤ 125°C, legacy chip (A grade) | 5 | |
| Line regulation | ΔVOUT(ΔVIN) | 0.007 | 0.014 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V, legacy chip | 6 | |
| Line regulation | ΔVOUT(ΔVIN) | 0.007 | 0.032 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C, legacy chip | 6 | |
| GND pin current | IGND | 65 | 95 | µA | IOUT = 0 mA, legacy chip | 6 | |
| GND pin current | IGND | 75 | 110 | µA | IOUT = 1 mA, legacy chip | 6 | |
| GND pin current | IGND | 350 | 600 | µA | IOUT = 50 mA, legacy chip | 6 | |
| GND pin current | IGND | 850 | 1500 | µA | IOUT = 150 mA, legacy chip | 6 | |
| GND pin current | IGND | 1500 | 2300 | µA | IOUT = 250 mA, legacy chip | 6 | |
| Shutdown current | 0.01 | 0.8 | µA | VON/OFF < 0.3 V, VIN = 16 V, legacy chip | 6 | ||
| Dropout voltage | VDO | 0.5 | 2.5 | mV | IOUT = 0 mA, legacy chip | 7 | |
| Dropout voltage | VDO | 5 | 9 | mV | IOUT = 1 mA, legacy chip | 7 | |
| Dropout voltage | VDO | 100 | 125 | mV | IOUT = 50 mA, legacy chip | 7 | |
| Dropout voltage | VDO | 260 | 325 | mV | IOUT = 150 mA, legacy chip | 7 | |
| Dropout voltage | VDO | 450 | 575 | mV | IOUT = 250 mA, legacy chip | 7 | |
| ON/OFF input voltage low | VON/OFF | 0.55 | V | Low = Output OFF, legacy chip | 7 | ||
| ON/OFF input voltage low | VON/OFF | 0.15 | V | Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C, legacy chip | 7 | ||
| ON/OFF input voltage high | VON/OFF | 1.4 | V | High = Output ON, legacy chip | 7 | ||
| ON/OFF input voltage high | VON/OFF | 1.6 | V | High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C, legacy chip | 7 | ||
| Continuous input voltage range | VIN | -0.3 | 16 | V | Legacy chip | 4 | |
| Output voltage range | VOUT | -0.3 | 9 | V | Legacy chip | 4 | |
| ON/OFF pin voltage range | VON/OFF | -0.3 | 16 | V | Legacy chip | 4 | |
| Operating junction temperature | TJ | -55 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Supply input voltage | VIN | 2.2 | 16 | V | Legacy chip | 4 | |
| Output voltage | VOUT | 1.2 | 10 | V | Legacy chip | 4 | |
| Enable voltage | VON/OFF | 0 | V | Legacy chip, upper limit is VIN | 4 | ||
| Output current | IOUT | 0 | 250 | mA | 4 | ||
| Output capacitance | COUT | 2.2 | 4.7 | µF | Legacy chip | 4 | |
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 169.7 | °C/W | Legacy chip, DBV (SOT-23-5), 5 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 122.6 | °C/W | Legacy chip, DBV (SOT-23-5), 5 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 29.9 | °C/W | Legacy chip, DBV (SOT-23-5), 5 pins | 5 | ||
| Junction-to-board characterization parameter | ψJB | 29.4 | °C/W | Legacy chip, DBV (SOT-23-5), 5 pins | 5 |
CAD (KiCad official)
- Symbol:
LP2992AIM5X-5.0 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
lp2992aim5x-5-0-etched.step/lp2992aim5x-5-0-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lp2992aim5x-5-0.step/lp2992aim5x-5-0.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (44 pp, sha256
2c240dff2d391d67, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).