component

LP2981AIM5-3.3

Public Made by Adom

by adom

Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)lp2981aim5-3.3factory-2.0.0extractor-text

Verified LP2981AIM5-3.3

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 5 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LP2981AIM5-3.3 · SOT-23-5 · 5 pins
  • ✓copper: 5 copper pads, none touching another net
  • ✓datasheet: all 5 pin names found in the 43-page datasheet
  • ✓distributor: lcsc C130187, digikey 2156-LP2981AIM5-3.3-ND, mouser 926-LP2981AIM5-33
  • ✓family: SOT-23-5
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-lxby8nb_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 5 pins = 5 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 5 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lp2981aim5-3-3.kicad_sym✓ lp2981aim5-3-3.kicad_mod✓ lp2981aim5-3-3.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers lp2981aim5-3-3: viewers · Ray 1d ago
lp2981aim5-3-3-etched.glb Publish 0.1.0 · Ray 1d ago
lp2981aim5-3-3-etched.step lp2981aim5-3-3: factory component page (tier=mfr) · Ray 1d ago
lp2981aim5-3-3-hero.glb lp2981aim5-3-3: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
lp2981aim5-3-3-hero.overlay.json Publish 0.1.0 · Ray 1d ago
lp2981aim5-3-3.glb Publish 0.1.0 · Ray 1d ago
lp2981aim5-3-3.kicad_mod Publish 0.1.0 · Ray 1d ago
lp2981aim5-3-3.kicad_sym Publish 0.1.0 · Ray 1d ago
lp2981aim5-3-3.lbr Publish 0.1.0 · Ray 1d ago
lp2981aim5-3-3.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 5 pins · Ray 1d ago

LP2981AIM5-3.3

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

LP2981AIM5-3.3 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply pin; use a capacitor of 1µF or larger from this pin to ground.
2 GND power_in Common ground (device substrate).
3 ON/OFF input Enable pin for the LDO; driving it high enables the device and driving it low disables it, with thresholds listed in the Electrical Characteristics table.
4 NC unconnected Reserved for post-packaging factory calibration of VOUT accuracy; must be left floating and not connected to any potential or ground.
5 OUT power_out Regulator output; use a capacitor of 2.2µF or larger from this pin to ground, with nominal output capacitance greater than 1µF.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Continuous input voltage range (legacy chip) VIN -0.3 16 V 4
Output voltage range (legacy chip) VOUT -0.3 9 V 4
ON/OFF pin voltage range (legacy chip) VON/OFF -0.3 16 V 4
Input-output voltage (legacy chip) VIN, VOUT -0.3 16 V 4
Operating junction temperature TJ -55 150 °C 4
Storage temperature Tstg -65 150 °C 4
Supply input voltage (legacy chip) VIN 2.1 16 V 4
Input-output differential (legacy chip) VIN, VOUT 0.7 11 V 4
Enable voltage (legacy chip) VON/OFF 0 V upper limit printed as VIN 4
Output current IOUT 0 100 mA 4
Input capacitor CIN 1 µF values assumed to derate to 50% of nominal 4
Output capacitor (legacy chip) COUT 2.2 4.7 µF 4
Operating junction temperature TJ -40 125 °C 4
Output voltage tolerance (legacy chip, A grade) ΔVOUT -0.75 0.75 % IL = 1 mA 5
Output voltage tolerance (legacy chip, A grade) ΔVOUT -1 1 % 1 mA < IL < 100 mA 5
Output voltage tolerance (legacy chip, A grade) ΔVOUT -2.5 2.5 % 1 mA < IL < 100 mA, -40°C ≤ TJ ≤ 125°C 5
Line regulation (legacy chip) ΔVOUT(ΔVIN) 0.007 0.014 %/V VO(NOM) + 1 V ≤ VIN ≤ 16 V 5
Line regulation (legacy chip) ΔVOUT(ΔVIN) 0.007 0.032 %/V VO(NOM) + 1 V ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C 5
Dropout voltage (legacy chip) VIN - VOUT 1 3 mV IOUT = 0 mA 6
Dropout voltage (legacy chip) VIN - VOUT 5 mV IOUT = 0 mA, -40°C ≤ TJ ≤ 125°C 6
Dropout voltage (legacy chip) VIN - VOUT 7 10 mV IOUT = 1 mA 6
Dropout voltage (legacy chip) VIN - VOUT 15 mV IOUT = 1 mA, -40°C ≤ TJ ≤ 125°C 6
Dropout voltage (legacy chip) VIN - VOUT 70 100 mV IOUT = 25 mA 6
Dropout voltage (legacy chip) VIN - VOUT 150 mV IOUT = 25 mA, -40°C ≤ TJ ≤ 125°C 6
Dropout voltage (legacy chip) VIN - VOUT 200 250 mV IOUT = 100 mA 6
Dropout voltage (legacy chip) VIN - VOUT 375 mV IOUT = 100 mA, -40°C ≤ TJ ≤ 125°C 6
GND pin current (legacy chip) IGND 65 95 µA IOUT = 0 mA 6
GND pin current (legacy chip) IGND 125 µA IOUT = 0 mA, -40°C ≤ TJ ≤ 125°C 6
GND pin current (legacy chip) IGND 80 110 µA IOUT = 1 mA 6
GND pin current (legacy chip) IGND 170 µA IOUT = 1 mA, -40°C ≤ TJ ≤ 125°C 6
GND pin current (legacy chip) IGND 200 300 µA IOUT = 25 mA 6
GND pin current (legacy chip) IGND 550 µA IOUT = 25 mA, -40°C ≤ TJ ≤ 125°C 6
GND pin current (legacy chip) IGND 600 800 µA IOUT = 100 mA 6
GND pin current (legacy chip) IGND 1500 µA IOUT = 100 mA, -40°C ≤ TJ ≤ 125°C 6
GND pin current in shutdown (legacy chip) IGND 0.01 0.8 µA VON/OFF < 0.3 V, VIN = 16 V 6
GND pin current in shutdown (legacy chip) IGND 0.05 2 µA VON/OFF < 0.15 V, VIN = 16 V, -40°C ≤ TJ ≤ 125°C 6
Short output current (legacy chip) IO(SC) 150 mA RL = 0 Ω (steady state) 6
ON/OFF input voltage low (legacy chip) VON/OFF 0.5 V Low = Output OFF 7
ON/OFF input voltage low (legacy chip) VON/OFF 0.15 V Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C 7
ON/OFF input voltage high (legacy chip) VON/OFF 1.4 V High = Output ON 7
ON/OFF input voltage high (legacy chip) VON/OFF 1.6 V High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C 7
ON/OFF input current (legacy chip) ION/OFF 0.01 µA VON/OFF = 0 V 7
ON/OFF input current (legacy chip) ION/OFF -1 µA VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C 7
ON/OFF input current (legacy chip) ION/OFF 5 µA VON/OFF = 5 V 7
ON/OFF input current (legacy chip) ION/OFF 15 µA VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C 7
Peak output current (legacy chip A version) IO(PK) 150 400 mA VOUT ≥ VO(NOM) -5% (steady state) 7
Ripple rejection (legacy chip) ΔVO/ΔVIN 63 dB f = 1 kHz, COUT = 10 µF 7
Output noise voltage (legacy chip) Vn 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA 7
Junction-to-ambient thermal resistance (legacy chip DBV) RθJA 175.7 °C/W 5
Junction-to-case (top) thermal resistance (legacy chip DBV) RθJC(top) 78 °C/W 5
Junction-to-board thermal resistance (legacy chip DBV) RθJB 30.8 °C/W 5
Junction-to-top characterization parameter (legacy chip DBV) ψJT 2.8 °C/W 5
Junction-to-board characterization parameter (legacy chip DBV) ψJB 30.3 °C/W 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, 30

CAD (KiCad official)

  • Symbol: LP2981AIM5-3.3
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: lp2981aim5-3-3-etched.step / lp2981aim5-3-3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp2981aim5-3-3.step / lp2981aim5-3-3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (43 pp, sha256 4edc0bbf3eaa25d3, retrieved 2026-11-05, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF