component
LP2981-50DBVR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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lp2981-50dbvr: specified limits as data (metadata.characteristics, 57 rows from the datasheet)
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LP2981-50DBVR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
LP2981-50DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | Input supply pin. Use a capacitor with a value of 1µF or larger from this pin to ground. |
| 2 | GND | power_in | Common ground (device substrate). |
| 3 | ON/OFF | input | Enable pin for the LDO. Driving the ON/OFF pin high enables the device; driving this pin low disables the device. Tie this pin to VIN if unused. |
| 4 | NC | unconnected | Do not connect. |
| 5 | OUT | output | Output of the regulator. Use a capacitor with a value of 2.2µF or larger from this pin to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Continuous input voltage range (legacy chip) | VIN | -0.3 | 16 | V | 3 | ||
| Continuous input voltage range (new chip) | VIN | -0.3 | 18 | V | 3 | ||
| Output voltage range (legacy chip) | VOUT | -0.3 | 9 | V | 3 | ||
| ON/OFF pin voltage range (legacy chip) | VON/OFF | -0.3 | 16 | V | 3 | ||
| ON/OFF pin voltage range (new chip) | VON/OFF | -0.3 | 18 | V | 3 | ||
| Input-output voltage (legacy chip) | VIN - VOUT | -0.3 | 16 | V | 3 | ||
| Input-output voltage (new chip) | VIN - VOUT | -0.3 | 18 | V | 3 | ||
| Operating junction temperature | TJ | -55 | 150 | °C | 3 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Supply input voltage (legacy chip) | VIN | 2.2 | 16 | V | 4 | ||
| Supply input voltage (new chip) | VIN | 2.5 | 16 | V | 4 | ||
| Input-output differential (legacy chip) | VIN - VOUT | 0.7 | 11 | V | 4 | ||
| Input-output differential (new chip) | VIN - VOUT | 0 | 16 | V | 4 | ||
| Output voltage (new chip) | VOUT | 1.2 | 5 | V | 4 | ||
| Enable voltage (legacy chip) | VON/OFF | 0 | V | 4 | |||
| Enable voltage (new chip) | VON/OFF | 0 | 16 | V | 4 | ||
| Output current | IOUT | 0 | 100 | mA | 4 | ||
| Input capacitor | CIN | 1 | µF | 4 | |||
| Output capacitor (legacy chip) | COUT | 3.3 | µF | 4 | |||
| Output capacitance (new chip) | COUT | 1 | 2.2 | 200 | µF | 4 | |
| Output capacitor ESR (new chip) | COUT ESR | 0 | 1 | Ω | 4 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance (legacy chip) | RθJA | 205.2 | °C/W | JEDEC 2s2p PCB | 4 | ||
| Junction-to-ambient thermal resistance (new chip) | RθJA | 178.6 | °C/W | JEDEC 2s2p PCB | 4 | ||
| Junction-to-case (top) thermal resistance (legacy chip) | RθJC(top) | 11.83 | °C/W | JEDEC 2s2p PCB | 4 | ||
| Junction-to-case (top) thermal resistance (new chip) | RθJC(top) | 77.9 | °C/W | JEDEC 2s2p PCB | 4 | ||
| Junction-to-board thermal resistance (legacy chip) | RθJB | 37.7 | °C/W | JEDEC 2s2p PCB | 4 | ||
| Junction-to-board thermal resistance (new chip) | RθJB | 47.2 | °C/W | JEDEC 2s2p PCB | 4 | ||
| Output voltage tolerance (standard grade, legacy chip) | ∆VOUT | -1.25 | 1.25 | % | IL = 1 mA, legacy chip (standard grade) | 5 | |
| Output voltage tolerance (new chip) | ∆VOUT | -0.5 | 0.5 | % | IL = 1 mA, new chip | 5 | |
| Output voltage tolerance (standard grade, legacy chip) | ∆VOUT | -2 | 2 | % | 1 mA < IL < 100 mA, legacy chip (standard grade) | 5 | |
| Output voltage tolerance (new chip) | ∆VOUT | -1 | 1 | % | 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, new chip | 5 | |
| Output voltage tolerance (standard grade, legacy chip) | ∆VOUT | -3.5 | 3.5 | % | 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, legacy chip (standard grade) | 5 | |
| Line regulation (legacy chip) | ΔVOUT(ΔVIN) | 0.007 | 0.014 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V | 5 | |
| Line regulation (new chip) | ΔVOUT(ΔVIN) | 0.002 | 0.014 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V | 5 | |
| Line regulation (legacy chip) | ΔVOUT(ΔVIN) | 0.007 | 0.032 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C | 5 | |
| Line regulation (new chip) | ΔVOUT(ΔVIN) | 0.002 | 0.032 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C | 5 | |
| Load regulation (new chip) | ΔVOUT(ΔILOAD) | 0.1 | 0.5 | %/A | 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V | 5 | |
| Dropout voltage (legacy chip) | VIN - VOUT | 1 | 3 | mV | IOUT = 0 mA, legacy chip | 5 | |
| Dropout voltage (new chip) | VIN - VOUT | 1 | 2.75 | mV | IOUT = 0 mA, new chip | 5 | |
| Dropout voltage (legacy chip) | VIN - VOUT | 7 | 10 | mV | IOUT = 1 mA, legacy chip | 5 | |
| Dropout voltage (new chip) | VIN - VOUT | 11.5 | 14 | mV | IOUT = 1 mA, new chip | 5 | |
| Dropout voltage (legacy chip) | VIN - VOUT | 70 | 100 | mV | IOUT = 25 mA, legacy chip | 5 | |
| Dropout voltage (new chip) | VIN - VOUT | 110 | 132 | mV | IOUT = 25 mA, new chip | 5 | |
| Dropout voltage (legacy chip) | VIN - VOUT | 200 | 250 | mV | IOUT = 100 mA, legacy chip | 5 | |
| Dropout voltage (new chip) | VIN - VOUT | 160 | 175 | mV | IOUT = 100 mA, new chip | 5 | |
| GND pin current (legacy chip) | IGND | 65 | 95 | µA | IOUT = 0 mA, legacy chip | 6 | |
| GND pin current (new chip) | IGND | 69 | 95 | µA | IOUT = 0 mA, new chip | 6 | |
| GND pin current (legacy chip) | IGND | 80 | 110 | µA | IOUT = 1 mA, legacy chip | 6 | |
| GND pin current (new chip) | IGND | 78 | 110 | µA | IOUT = 1 mA, new chip | 6 | |
| GND pin current (legacy chip) | IGND | 200 | 300 | µA | IOUT = 25 mA, legacy chip | 6 | |
| GND pin current (new chip) | IGND | 225 | 295 | µA | IOUT = 25 mA, new chip | 6 | |
| GND pin current (legacy chip) | IGND | 600 | 1000 | µA | IOUT = 100 mA, legacy chip | 6 | |
| GND pin current (new chip) | IGND | 620 | 790 | µA | IOUT = 100 mA, new chip | 6 | |
| GND pin current with output disabled (legacy chip) | IGND | 0.01 | 0.8 | µA | VON/OFF < 0.3 V, VIN = 16 V, legacy chip | 6 | |
| GND pin current with output disabled (new chip) | IGND | 1.25 | 1.75 | µA | VON/OFF < 0.3 V, VIN = 16 V, new chip | 6 | |
| GND pin current with output disabled (new chip) | IGND | 1.12 | 2.75 | µA | VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C, new chip | 6 |
CAD (KiCad official)
- Symbol:
LP2981-50DBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
lp2981-50dbvr-etched.step/lp2981-50dbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lp2981-50dbvr.step/lp2981-50dbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (35 pp, sha256
f9a14a5370d16829, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LP2981-50DBVR
**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
LP2981-50DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | Input supply pin. Use a capacitor with a value of 1µF or larger from this pin to ground. |
| 2 | GND | power_in | Common ground (device substrate). |
| 3 | ON/OFF | input | Enable pin for the LDO. Driving the ON/OFF pin high enables the device; driving this pin low disables the device. Tie this pin to VIN if unused. |
| 4 | NC | unconnected | Do not connect. |
| 5 | OUT | output | Output of the regulator. Use a capacitor with a value of 2.2µF or larger from this pin to ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Continuous input voltage range (legacy chip) | VIN | -0.3 | | 16 | V | | 3 |
| Continuous input voltage range (new chip) | VIN | -0.3 | | 18 | V | | 3 |
| Output voltage range (legacy chip) | VOUT | -0.3 | | 9 | V | | 3 |
| ON/OFF pin voltage range (legacy chip) | VON/OFF | -0.3 | | 16 | V | | 3 |
| ON/OFF pin voltage range (new chip) | VON/OFF | -0.3 | | 18 | V | | 3 |
| Input-output voltage (legacy chip) | VIN - VOUT | -0.3 | | 16 | V | | 3 |
| Input-output voltage (new chip) | VIN - VOUT | -0.3 | | 18 | V | | 3 |
| Operating junction temperature | TJ | -55 | | 150 | °C | | 3 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| Supply input voltage (legacy chip) | VIN | 2.2 | | 16 | V | | 4 |
| Supply input voltage (new chip) | VIN | 2.5 | | 16 | V | | 4 |
| Input-output differential (legacy chip) | VIN - VOUT | 0.7 | | 11 | V | | 4 |
| Input-output differential (new chip) | VIN - VOUT | 0 | | 16 | V | | 4 |
| Output voltage (new chip) | VOUT | 1.2 | | 5 | V | | 4 |
| Enable voltage (legacy chip) | VON/OFF | 0 | | | V | | 4 |
| Enable voltage (new chip) | VON/OFF | 0 | | 16 | V | | 4 |
| Output current | IOUT | 0 | | 100 | mA | | 4 |
| Input capacitor | CIN | 1 | | | µF | | 4 |
| Output capacitor (legacy chip) | COUT | 3.3 | | | µF | | 4 |
| Output capacitance (new chip) | COUT | 1 | 2.2 | 200 | µF | | 4 |
| Output capacitor ESR (new chip) | COUT ESR | 0 | | 1 | Ω | | 4 |
| Operating junction temperature | TJ | -40 | | 125 | °C | | 4 |
| Junction-to-ambient thermal resistance (legacy chip) | RθJA | | 205.2 | | °C/W | JEDEC 2s2p PCB | 4 |
| Junction-to-ambient thermal resistance (new chip) | RθJA | | 178.6 | | °C/W | JEDEC 2s2p PCB | 4 |
| Junction-to-case (top) thermal resistance (legacy chip) | RθJC(top) | | 11.83 | | °C/W | JEDEC 2s2p PCB | 4 |
| Junction-to-case (top) thermal resistance (new chip) | RθJC(top) | | 77.9 | | °C/W | JEDEC 2s2p PCB | 4 |
| Junction-to-board thermal resistance (legacy chip) | RθJB | | 37.7 | | °C/W | JEDEC 2s2p PCB | 4 |
| Junction-to-board thermal resistance (new chip) | RθJB | | 47.2 | | °C/W | JEDEC 2s2p PCB | 4 |
| Output voltage tolerance (standard grade, legacy chip) | ∆VOUT | -1.25 | | 1.25 | % | IL = 1 mA, legacy chip (standard grade) | 5 |
| Output voltage tolerance (new chip) | ∆VOUT | -0.5 | | 0.5 | % | IL = 1 mA, new chip | 5 |
| Output voltage tolerance (standard grade, legacy chip) | ∆VOUT | -2 | | 2 | % | 1 mA < IL < 100 mA, legacy chip (standard grade) | 5 |
| Output voltage tolerance (new chip) | ∆VOUT | -1 | | 1 | % | 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, new chip | 5 |
| Output voltage tolerance (standard grade, legacy chip) | ∆VOUT | -3.5 | | 3.5 | % | 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, legacy chip (standard grade) | 5 |
| Line regulation (legacy chip) | ΔVOUT(ΔVIN) | | 0.007 | 0.014 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V | 5 |
| Line regulation (new chip) | ΔVOUT(ΔVIN) | | 0.002 | 0.014 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V | 5 |
| Line regulation (legacy chip) | ΔVOUT(ΔVIN) | | 0.007 | 0.032 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C | 5 |
| Line regulation (new chip) | ΔVOUT(ΔVIN) | | 0.002 | 0.032 | %/V | VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C | 5 |
| Load regulation (new chip) | ΔVOUT(ΔILOAD) | | 0.1 | 0.5 | %/A | 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V | 5 |
| Dropout voltage (legacy chip) | VIN - VOUT | | 1 | 3 | mV | IOUT = 0 mA, legacy chip | 5 |
| Dropout voltage (new chip) | VIN - VOUT | | 1 | 2.75 | mV | IOUT = 0 mA, new chip | 5 |
| Dropout voltage (legacy chip) | VIN - VOUT | | 7 | 10 | mV | IOUT = 1 mA, legacy chip | 5 |
| Dropout voltage (new chip) | VIN - VOUT | | 11.5 | 14 | mV | IOUT = 1 mA, new chip | 5 |
| Dropout voltage (legacy chip) | VIN - VOUT | | 70 | 100 | mV | IOUT = 25 mA, legacy chip | 5 |
| Dropout voltage (new chip) | VIN - VOUT | | 110 | 132 | mV | IOUT = 25 mA, new chip | 5 |
| Dropout voltage (legacy chip) | VIN - VOUT | | 200 | 250 | mV | IOUT = 100 mA, legacy chip | 5 |
| Dropout voltage (new chip) | VIN - VOUT | | 160 | 175 | mV | IOUT = 100 mA, new chip | 5 |
| GND pin current (legacy chip) | IGND | | 65 | 95 | µA | IOUT = 0 mA, legacy chip | 6 |
| GND pin current (new chip) | IGND | | 69 | 95 | µA | IOUT = 0 mA, new chip | 6 |
| GND pin current (legacy chip) | IGND | | 80 | 110 | µA | IOUT = 1 mA, legacy chip | 6 |
| GND pin current (new chip) | IGND | | 78 | 110 | µA | IOUT = 1 mA, new chip | 6 |
| GND pin current (legacy chip) | IGND | | 200 | 300 | µA | IOUT = 25 mA, legacy chip | 6 |
| GND pin current (new chip) | IGND | | 225 | 295 | µA | IOUT = 25 mA, new chip | 6 |
| GND pin current (legacy chip) | IGND | | 600 | 1000 | µA | IOUT = 100 mA, legacy chip | 6 |
| GND pin current (new chip) | IGND | | 620 | 790 | µA | IOUT = 100 mA, new chip | 6 |
| GND pin current with output disabled (legacy chip) | IGND | | 0.01 | 0.8 | µA | VON/OFF < 0.3 V, VIN = 16 V, legacy chip | 6 |
| GND pin current with output disabled (new chip) | IGND | | 1.25 | 1.75 | µA | VON/OFF < 0.3 V, VIN = 16 V, new chip | 6 |
| GND pin current with output disabled (new chip) | IGND | | 1.12 | 2.75 | µA | VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C, new chip | 6 |
## CAD (KiCad official)
- Symbol: `LP2981-50DBVR`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `lp2981-50dbvr-etched.step` / `lp2981-50dbvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lp2981-50dbvr.step` / `lp2981-50dbvr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lp2981a) (35 pp, sha256 `f9a14a5370d16829`, retrieved 2026-09-23, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lp2981-50dbvr-datasheet.pdf)