component

LP2980AIM5X-4.7

Public Made by Adom

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)lp2980aim5x-4.7factory-2.0.0extractor-text

Verified LP2980AIM5X-4.7

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 5 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LP2980AIM5X-4.7 · SOT-23-5 · 5 pins
  • ✓copper: 5 copper pads, none touching another net
  • ✓datasheet: all 5 pin names found in the 39-page datasheet
  • ✓distributor: lcsc C2863256, digikey LP2980AIM5X-4.7TR-ND, mouser 926-LP2980AIM5X-47
  • ✓family: SOT-23-5
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-xf34krqw/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 5 pins = 5 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 5 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lp2980aim5x-4-7.kicad_sym✓ lp2980aim5x-4-7.kicad_mod✓ lp2980aim5x-4-7.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 6h ago
viewers lp2980aim5x-4-7: viewers · Ray 6h ago
lp2980aim5x-4-7-etched.glb Publish 0.1.0 · Ray 6h ago
lp2980aim5x-4-7-etched.step lp2980aim5x-4-7: factory component page (tier=mfr) · Ray 6h ago
lp2980aim5x-4-7-hero.glb lp2980aim5x-4-7: hero GLB from the etched model (keeps the MPN mark) · Ray 6h ago
lp2980aim5x-4-7-hero.overlay.json Publish 0.1.0 · Ray 6h ago
lp2980aim5x-4-7.glb Publish 0.1.0 · Ray 6h ago
lp2980aim5x-4-7.kicad_mod Publish 0.1.0 · Ray 6h ago
lp2980aim5x-4-7.kicad_sym Publish 0.1.0 · Ray 6h ago
lp2980aim5x-4-7.lbr Publish 0.1.0 · Ray 6h ago
lp2980aim5x-4-7.step Publish 0.1.0 · Ray 6h ago
package.json Publish 0.1.0 · Ray 6h ago
page.json Set visibility: public · Ray 6h ago
README.md Publish 0.1.0 · Ray 6h ago
verification.json Verified: Published by the parts factory: tier mfr, 5 pins · Ray 6h ago

LP2980AIM5X-4.7

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

LP2980AIM5X-4.7 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply pin; use a capacitor of 1µF or larger from this pin to ground.
2 GND power_in Common ground (device substrate).
3 ON/OFF input Enable pin for the LDO: driving it high enables the device and driving it low disables it, with thresholds listed in the Electrical Characteristics table; tie to VIN if unused.
4 N/C unconnected Do not connect: pin 4 is reserved for factory calibration of VOUT accuracy and must be left floating, not tied to any potential or ground.
5 OUT power_out Output of the regulator; use a capacitor of 2.2µF or larger from this pin to ground, with nominal output capacitance greater than 1µF.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Continuous input voltage range (legacy chip) VIN -0.3 16 V legacy chip; all voltages with respect to GND 3
Continuous input voltage range (new chip) VIN -0.3 18 V new chip; all voltages with respect to GND 3
Output voltage range (legacy chip) VOUT -0.3 9 V legacy chip 3
ON/OFF pin voltage range (legacy chip) VON/OFF -0.3 16 V legacy chip 3
ON/OFF pin voltage range (new chip) VON/OFF -0.3 18 V new chip 3
Operating junction temperature TJ -55 150 °C 3
Storage temperature Tstg -65 150 °C 3
Supply input voltage (legacy chip) VIN 2.2 16 V legacy chip 3
Supply input voltage (new chip) VIN 2.5 16 V new chip 3
Output voltage (legacy chip) VOUT 1.2 10 V legacy chip 3
Output voltage (new chip) VOUT 1.2 5 V new chip 3
Enable voltage (new chip) VON/OFF 0 16 V new chip 3
Output current IOUT 0 50 mA 3
Output capacitance (new chip) COUT 1 2.2 200 µF new chip; derated to 50% of nominal 3
Output capacitance (legacy chip) COUT 2.2 4.7 µF legacy chip 3
Output capacitor ESR (new chip) COUT ESR 0 1 Ω new chip 3
Operating junction temperature TJ -40 125 °C 3
Junction-to-ambient thermal resistance (legacy chip) RθJA 205.4 °C/W legacy chip, DBV (SOT23-5) 4
Junction-to-ambient thermal resistance (new chip) RθJA 178.6 °C/W new chip, DBV (SOT23-5) 4
Output voltage tolerance ΔVOUT -0.5 0.5 % IL = 1mA; legacy chip (A grade) 4
Output voltage tolerance ΔVOUT -0.75 0.75 % 1 mA ≤ IL ≤ 50 mA; legacy chip (A grade) 4
Output voltage tolerance ΔVOUT -2.5 2.5 % 1 mA ≤ IL ≤ 50 mA, -40°C ≤ TJ ≤ 125°C; legacy chip (A grade) 4
Output voltage tolerance ΔVOUT -1 1 % 1 mA ≤ IL ≤ 50 mA, -40°C ≤ TJ ≤ 125°C; new chip 4
Line regulation ΔVOUT(ΔVIN) 0.007 0.014 %/V VO(NOM) + 1 V ≤ VIN ≤ 16 V; legacy chip 4
Line regulation ΔVOUT(ΔVIN) 0.002 0.014 %/V VO(NOM) + 1 V ≤ VIN ≤ 16 V; new chip 4
Line regulation ΔVOUT(ΔVIN) 0.007 0.032 %/V VO(NOM) + 1 V ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C; legacy chip 4
Line regulation ΔVOUT(ΔVIN) 0.002 0.032 %/V VO(NOM) + 1 V ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C; new chip 4
Dropout voltage VIN - VOUT 1 3 mV IOUT = 0 mA; legacy chip 5
Dropout voltage VIN - VOUT 1 2.75 mV IOUT = 0 mA; new chip 5
Dropout voltage VIN - VOUT 7 10 mV IOUT = 1 mA; legacy chip 5
Dropout voltage VIN - VOUT 11.5 14 mV IOUT = 1 mA; new chip 5
Dropout voltage VIN - VOUT 40 60 mV IOUT = 10 mA; legacy chip 5
Dropout voltage VIN - VOUT 98 115 mV IOUT = 10 mA; new chip 5
Dropout voltage VIN - VOUT 120 150 mV IOUT = 50 mA; legacy chip 5
Dropout voltage VIN - VOUT 120 145 mV IOUT = 50 mA; new chip 5
GND pin current IGND 65 95 uA IOUT = 0 mA; legacy chip 6
GND pin current IGND 69 95 uA IOUT = 0 mA; new chip 6
GND pin current IGND 75 110 uA IOUT = 1 mA; legacy chip 6
GND pin current IGND 78 110 uA IOUT = 1 mA; new chip 6
GND pin current IGND 120 220 uA IOUT = 10 mA; legacy chip 6
GND pin current IGND 175 210 uA IOUT = 10 mA; new chip 6
GND pin current IGND 350 600 uA IOUT = 50 mA; legacy chip 6
GND pin current IGND 380 440 uA IOUT = 50 mA; new chip 6
Shutdown GND pin current IGND 0 1 uA VON/OFF < 0.18 V, -40°C ≤ TJ ≤ 125°C; legacy chip 6
Shutdown GND pin current IGND 1.12 2.25 uA VON/OFF < 0.18 V, -40°C ≤ TJ ≤ 125°C; new chip 6
Peak output current IO(PK) 110 150 mA VOUT ≥ VO(NOM) -5% (steady state); legacy chip 6
ON/OFF input voltage low VON/OFF 0.15 V Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C; new chip 6
ON/OFF input voltage high VON/OFF 1.6 V High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, -40°C ≤ TJ ≤ 125°C; new chip 6
Ripple rejection ΔVO/ΔVIN 63 dB f = 1 kHz, COUT = 10 µF; legacy chip 6
Ripple rejection ΔVO/ΔVIN 75 dB f = 1 kHz, COUT = 10 µF; new chip 6
Ripple rejection ΔVO/ΔVIN 45 dB f = 100 kHz, ILOAD = 50mA; new chip 6
Output noise voltage Vn 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 10uF, VOUT = 3.3V, ILOAD = 50mA; legacy chip 6
Output noise voltage Vn 140 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2uF, VOUT = 3.3V, ILOAD = 50mA; new chip 6
Output noise voltage Vn 50 µVRMS Bandwidth = 10 Hz to 100 kHz, COUT = 2.2uF, VOUT = 3.3V, ILOAD = 50mA; new chip 6
Thermal shutdown threshold Tsd+ 170 °C Shutdown, temperature increasing; new chip 7
Thermal shutdown reset threshold Tsd- 150 °C Reset, temperature decreasing; new chip 7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper capacitors, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side, copper surface. Using vias and long traces to create LDO circuit connections is strongly 26

CAD (KiCad official)

  • Symbol: LP2980AIM5X-4.7
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: lp2980aim5x-4-7-etched.step / lp2980aim5x-4-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lp2980aim5x-4-7.step / lp2980aim5x-4-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 134be8e046145f40, retrieved 2026-11-05, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF