# LP2305LT1G

**LRC** · MOSFETs · SOT-23

LP2305LT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate; gate-to-source voltage limited to ±12 V, threshold -0.7 to -1.3 V at ID = -250 μA. |
| 2 | S | passive | Source of the P-channel MOSFET; drain-to-source voltage rating is -30 V. |
| 3 | D | passive | Drain; continuous drain current -4.2 A, pulsed -30 A, VDSS -30 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-to-Source Voltage | VDSS |  |  | -30 | V | Ta = 25℃ | 1 |
| Gate-to-Source Voltage | VGS | -12 |  | 12 | V | Ta = 25℃ | 1 |
| Continuous Drain Current | ID |  |  | -4.2 | A | Ta = 25℃ | 1 |
| Pulsed Drain Current | IDM |  |  | -30 | A | Ta = 25℃, Note 1: pulse width limited by maximum junction temperature | 1 |
| Total Power Dissipation | PD |  |  | 1.4 | W | Ta = 25℃ | 1 |
| Operating and Storage Temperature Range | TJ, Tstg | -55 |  | 150 | °C |  | 1 |
| Thermal Resistance Junction to Ambient | RθJA |  |  | 140 | °C/W | Note 2: 1-in2 2oz Cu PCB board | 1 |
| Drain-to-Source Breakdown Voltage | V(BR)DSS | -30 |  |  | V | VGS = 0 V, ID = -250 μA | 2 |
| Gate Threshold Voltage | VGS(TH) | -0.7 |  | -1.3 | V | VGS = VDS, ID =- 250 μA | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | -1 | μA | VDS=-24V, VGS=0V | 2 |
| Gate-to-Source Leakage Current | IGSS | -100 |  | 100 | nA | VDS = 0 V, VGS = ±12 V | 2 |
| Drain-to-Source On Resistance (VGS = -10 V) | RDS(on) |  | 53 | 70 | mΩ | VGS = -10V, ID = -4.2 A | 2 |
| Drain-to-Source On Resistance (VGS = -4.5 V) | RDS(on) |  | 64 | 85 | mΩ | VGS = -4.5 V, ID = -4 A | 2 |
| Drain-to-Source On Resistance (VGS = -2.5 V) | RDS(on) |  | 86 | 130 | mΩ | VGS = -2.5 V, ID = -1 A | 2 |
| Forward Diode Voltage | VSD |  | -1 |  | V | VGS = 0 V, ISD = -1A | 2 |
| Forward Transconductance | gFS | 7 | 11 |  | S | VDS = -5.0 V, ID = -5 A | 2 |

## CAD (KiCad official)

- Symbol: `LP2305LT1G`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `lp2305lt1g-etched.step` / `lp2305lt1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lp2305lt1g.step` / `lp2305lt1g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [LRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586182481380839424) (4 pp, sha256 `92b286dda0b82154`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lp2305lt1g-datasheet.pdf)