# LN8322SR-G

**NATLINEAR** · Gate Drive ICs · SOP-8

LN8322SR-G from NATLINEAR, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST | power_in | High-side floating bootstrap supply pin, connected to SW through the bootstrap capacitor (at least 100nF, abs max 30V). |
| 2 | PWM | input | Control input: PWM high gives DRVH high and DRVL low, PWM low gives DRVH low and DRVL high (high threshold 2.0V min, low threshold 0.8V max, abs max 6V). |
| 3 | EN | input | Enable input: high enables the chip, low shuts it down and holds DRVH and DRVL low (threshold 2.0V/0.8V, abs max 6V, pulled to GND in VCC UVLO). |
| 4 | VCC | power_in | Supply input of 4.5V to 13.2V with an external 0.1uF bypass capacitor to ground (application section recommends at least 1uF low-ESR). |
| 5 | DRVL | output | Low-side driver output connected to the gate of the low-side MOSFET (abs max VCC+0.3V). |
| 6 | GND | power_in | Ground. |
| 7 | SW | passive | High-side floating ground, connected to the source of the high-side MOSFET and the drain of the low-side MOSFET (abs max -5V to VBST+0.3V). |
| 8 | DRVH | output | High-side driver output connected to the gate of the high-side MOSFET (abs max VSW-0.3V to VBST+0.3V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | NATLINEAR |
| Package | SOP-8 |
| Category | Power Supply Chip |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC operating voltage | VCC | 4.5 |  | 13.2 | V |  | 4 |
| UVLO threshold | UVLO | 3.7 | 4.2 | 4.7 | V | VDD rising | 4 |
| VCC quiescent current | IQCC |  | 0.3 | 0.8 | mA | EN=GND | 4 |
| VCC operating current | ICC |  | 10 | 13 | mA | EN=High, PWM=OSC, FSW=100KHz, 3nF for DRVH & DRVL | 4 |
| PWM high threshold | VPWMH | 2 |  |  | V | PWM rising | 4 |
| PWM low threshold | VPWML |  |  | 0.8 | V | PWM falling | 4 |
| EN high threshold | VENH | 2 |  |  | V | EN rising | 4 |
| EN low threshold | VENL |  |  | 0.8 | V | EN falling | 4 |
| EN bias current | IEN | -1 |  | 1 | uA | Normal mode | 4 |
| EN pull-down current | IEN_SINK | 4 |  | 30 | mA | VCC UVLO | 4 |
| EN rising propagation delay | tpdhEN |  | 30 | 50 | ns | EN going from 0V to VENH to DRVL or DRVH rising to 10% | 4 |
| EN falling propagation delay | tpdlEN |  | 20 | 35 | ns | EN going from VENL to 0V to DRVL or DRVH falling to 90% | 4 |
| DRVH source resistance (12V) | RDRVH_SOURCE |  | 2 | 3 | Ω | BST-SW=12V, DRVH-SW=0.5V | 4 |
| DRVH sink resistance (12V) | RDRVH_SINK |  | 1 | 1.8 | Ω | BST-SW=12V, DRVH-SW=0.5V | 4 |
| DRVH rise time (12V) | trDRVH |  | 15 | 35 | ns | BST-SW=12V, Cload=3.0nF | 4 |
| DRVH fall time (12V) | tfDRVH |  | 10 | 25 | ns | BST-SW=12V, Cload=3.0nF | 4 |
| DRVH fall propagation delay (12V) | tpdlDRVH |  | 13 | 30 | ns | BST-SW=12V, Cload=3.0nF | 4 |
| DRVH source resistance (5V) | RDRVH_SOURCE |  | 3 | 5 | Ω | BST-SW=5V, DRVH-SW=0.5V | 4 |
| DRVH sink resistance (5V) | RDRVH_SINK |  | 2 | 4 | Ω | BST-SW=5V, DRVH-SW=0.5V | 4 |
| DRVL source resistance (12V) | RDRVL_SOURCE |  | 2 | 3 | Ω | VCC=12V, DRVL =0.5V | 5 |
| DRVL sink resistance (12V) | RDRVL_SINK |  | 0.7 | 1.5 | Ω | VCC=12V, DRVL =0.5V | 5 |
| DRVL rise time (12V) | trDRVL |  | 16 | 35 | ns | VCC=12V, Cload=3.0nF | 5 |
| DRVL fall time (12V) | tfDRVL |  | 10 | 25 | ns | VCC=12V, Cload=3.0nF | 5 |
| DRVL fall propagation delay (12V) | tpdlDRVL |  | 12 | 30 | ns | VCC=12V, Cload=3.0nF | 5 |
| DRVL source resistance (5V) | RDRVL_SOURCE |  | 3 | 5 | Ω | VCC=5V, DRVL =0.5V | 5 |
| DRVL sink resistance (5V) | RDRVL_SINK |  | 1.5 | 3 | Ω | VCC=5V, DRVL =0.5V | 5 |
| VCC voltage | VCC | -0.3 |  | 13.2 | V |  | 3 |
| BST voltage | VBST | -0.3 |  | 30 | V |  | 3 |
| SW voltage | VSW | -5 |  |  | V | max is VBST+0.3 | 3 |
| DRVL voltage | VDRVL | -0.3 |  |  | V | max is VCC+0.3 | 3 |
| EN voltage | VEN | -0.3 |  | 6 | V |  | 3 |
| PWM voltage | VPWM | -0.3 |  | 6 | V |  | 3 |
| Storage temperature | TSTG | -40 |  | 150 | ℃ |  | 3 |
| Operating junction temperature | TJ | -40 |  | 150 | ℃ |  | 3 |
| ESD HBM | VESD |  |  | 4000 | V | HBM | 3 |
| UVLO hysteresis | ΔUVLO |  | 0.2 |  | V | VDD falling | 4 |
| EN hysteresis | VHYS_EN |  | 0.3 |  | V |  | 4 |

## CAD (KiCad official)

- Symbol: `LN8322SR-G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `ln8322sr-g-etched.step` / `ln8322sr-g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ln8322sr-g.step` / `ln8322sr-g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [NATLINEAR datasheet](docs/ln8322sr-g-datasheet.pdf) (11 pp, sha256 `c175686631999231`, retrieved 2026-10-22, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ln8322sr-g-datasheet.pdf)