# LMX5069DL

**Wuxi Maxinmicro** · Surge Protection Devices (SPDs) · DFN-10L(3x3)

LMX5069DL from Wuxi Maxinmicro, in a DFN-10L(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SENSE | input | Current sense input: the voltage across the sense resistor RS is measured from VIN to this pin, and the load current is limited when that voltage reaches 55mV, which also activates the fault timer. |
| 2 | VIN | power_in | Positive supply input with a recommended operating range of 9 to 90V, where a small ceramic bypass capacitor placed close to this pin suppresses transients when the load current is switched off. |
| 3 | UVLO | input | Dual-function pin that shuts off the internal pass MOSFET when pulled down as an enable, and as an undervoltage lockout pin sets the UVLO trip point through an external resistor divider with a 2.5V typical threshold (2.25V to 2.75V). |
| 4 | OVLO | input | Overvoltage lockout input set by an external resistor divider from the system input voltage, with a 2.5V typical disable threshold and an internal 18µA current source providing hysteresis. |
| 5 | GND | power_in | Circuit ground. |
| 6 | Timer | passive | External timing capacitor pin that sets the insertion time delay, the fault timeout period and the restart timing, with the fault timer reaching 3.6V to declare a fault. |
| 7 | PWR | passive | Current limit set pin: an external resistor connected here, together with the sense resistor, sets the maximum power dissipation allowed in the external series pass MOSFET. |
| 8 | PGD | output | Open-drain active-low Power Good output that goes active when the MOSFET VDS falls below 1.5V and switches low when VDS rises above 2.5V, with a maximum output low voltage of 150mV at 2mA sink current. |
| 9 | OUT | input | Output feedback connected to the output rail (external MOSFET source), used internally to determine the MOSFET VDS for power limiting and to control the PGD indicator. |
| 10 | GATE | output | Gate drive output connected to the external MOSFET gate, typically 12V above the OUT pin when enabled, with a gate-to-OUT voltage of 10V to 14V and an internal 12V Zener limiting the gate-to-source voltage. |
| 11 | Thermal PAD | power_in | Exposed thermal pad, designated as ground. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Wuxi Maxinmicro |
| Package | DFN-10L(3x3) |
| Category | Circuit Protection |
| Pins | 11 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage |  | 9 |  | 90 | V |  | 1 |
| OVP, PWR, Timer voltage |  | 0 |  | 5 | V |  | 1 |
| Junction temperature |  | -40 |  | 125 | ℃ |  | 1 |
| VIN to GND |  | -0.3 |  | 108 | V |  | 1 |
| SENSE, OUT to GND |  | -0.3 |  | 108 | V |  | 1 |
| GATE to GND |  | -0.3 |  | 120 | V |  | 1 |
| OUT to GND |  | -0.3 |  | 108 | V | 1ms transient | 1 |
| OVP, PWR, Timer to GND |  | -0.3 |  | 7 | V |  | 1 |
| VIN to SENSE |  | -0.3 |  | 0.3 | V |  | 1 |
| Maximum junction temperature | TJMAX |  |  | 150 | ℃ |  | 1 |
| Storage temperature | Tstg | -65 |  | 150 | ℃ |  | 1 |
| Package thermal resistance, junction to ambient | RθJA |  |  | 50 | ℃/W | DFN3*3-10L package | 1 |
| Input voltage (VIN pin) | VIN | 8 |  | 90 | V |  | 5 |
| Supply current (on) | IQON |  | 300 | 650 | μA | UVLO>2.5V and OVLO<2.5V | 5 |
| Supply current (off) | IQOFF |  | 100 | 350 | μA | UVLO<2.5V | 5 |
| Insertion-time threshold | VINSERT | 5.5 | 6.5 | 7.5 | V |  | 5 |
| Enable threshold at VIN (VIN-enable) | VINEN | 6.8 |  | 8.5 | V |  | 5 |
| UVLO threshold voltage falling | VUVLOR | 2.25 | 2.5 | 2.75 | V |  | 5 |
| UVLO hysteresis current | UVLOHYS | 12 | 18 | 24 | μA | UVLO=1V | 5 |
| UVLO bias current | UVLOBIAS |  |  | 1 | μA | UVLO=48V | 5 |
| OVLO threshold voltage rising | VOVLOR | 2.25 | 2.5 | 2.75 | V |  | 5 |
| OVLO hysteresis current | OVLOHYS | 12 | 18 | 24 | µA | OVLO=3V | 5 |
| OVLO bias current | OVLOBIAS |  |  | 1 | µA | OVLO=2V | 5 |
| OUT bias current, disabled | IOUT_DIS |  |  | 50 | µA | Disabled, OUT = 0V, SENSE = VIN | 5 |
| OUT bias current, enabled | IOUT_EN |  |  | 11 | µA | Enabled, OUT=VIN | 5 |
| Gate source current | IGATE | 10 | 15 | 22 | µA | Normal operation | 5 |
| Gate sink current |  | 1.7 | 2 | 2.5 | mA | UVLO < 2.5V | 5 |
| Gate sink current |  | 45 | 230 | 300 | mA | VIN to SENSE = 150mV, GATE=5V | 5 |
| GATE-OUT voltage in normal operation | VGATE | 10 |  | 14 | V |  | 5 |
| Power limit sense voltage (VIN-SENSE) | PWRILM-1 | 19 | 25 | 31 | mV | SEN-OUT=48V, RPWR=150kΩ | 5 |
| Power limit sense voltage (VIN-SENSE) | PWRILM-2 |  |  | 25 | mV | SENSE-OUT=24V, RPWR=75 kΩ | 5 |
| Power pin current | IPWR | 17 | 20 | 23 | µA | PWR=2.5V | 5 |
| Over current threshold (VIN-VSENSE) | VCL | 48 | 55 | 65 | mV |  | 5 |
| SENSE input current, enabled | ISENSE |  |  | 8 | µA | Enable, OUT=SENSE | 5 |
| SENSE input current, disabled | ISENSE |  |  | 10 | µA | Disable, OUT=0V | 5 |
| Upper threshold, end of insertion time | VTMRH | 3.2 | 3.6 | 4 | V |  | 5 |
| Lower threshold, restart cycles | VTMRL | 0.5 | 0.8 | 1.1 | V | Restart cycles | 5 |
| Lower threshold, end of 8th cycle | VTMRL |  |  | 0.25 | V | End of 8th cycles | 5 |
| Insertion time current | ITIMER | 2 | 4 | 6 | µA | VIN=VINSERT | 5 |
| Sink current, end of insertion time |  | 0.7 |  | 2 | mA | Timer=2V | 5 |
| Fault detection current | ITIMER | 45 | 70 | 95 | µA |  | 5 |
| Fault sink current | ITIMER | 1.25 | 2.5 | 3.75 | µA |  | 5 |
| Fault restart duty cycle | DTFAULT |  |  | 0.5 | % |  | 5 |
| Threshold at SENSE-OUT, decreasing | PGDTH | 0.6 | 1.5 | 2.5 | V | Decreasing | 5 |
| Threshold at SENSE-OUT, increasing | PGDTH | 0.3 | 1.25 | 1.5 | V | Increasing, relative to decreasing threshold | 5 |
| Output low voltage | PGDVOL | 60 |  | 150 | mV | ISINK=2mA | 5 |
| Off leakage current | PGDIOH |  |  | 5 | µA | VPGD=80V | 5 |
| UVLO delay, rising | UVLODLY |  |  | 55 | µs | UVLO rising to GATE begin to rise | 6 |
| UVLO delay, falling | UVLODLY |  |  | 20 | µs | UVLO falling to GATE begin to fall | 6 |
| OVLO delay, rising | OVLODLY |  |  | 20 | µs | OVLO rising to GATE begin to fall | 6 |
| OVLO delay, falling | OVLODLY |  |  | 55 | µs | OVLO falling to GATE begin to rise | 6 |
| Response time for OCP | TCL |  |  | 50 | µs | VIN-SENSE stepped from 0V to 80mV | 6 |
| Response time | TCB |  |  | 1 | µs | VIN-SENSE stepped from 0V to 150mV, time to GATE low, no load | 6 |
| Fault to GATE low delay | tFAULT |  |  | 12 | µs | Timer pin reaches 3.6V | 6 |

## CAD (KiCad official)

- Symbol: `LMX5069DL`
- Footprint: `Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm`
- 3D model: DFN-10L(3x3) (KiCad packages3D, STEP)
- 3D model files: `lmx5069dl-etched.step` / `lmx5069dl-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmx5069dl.step` / `lmx5069dl.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Wuxi Maxinmicro datasheet](docs/lmx5069dl-datasheet.pdf) (19 pp, sha256 `b5c8b12e720764a3`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lmx5069dl-datasheet.pdf)