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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LMX2820RTCR

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · VQFN-48(7x7)

LMX2820RTCR from Texas Instruments, in a VQFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CE	input	Chip Enable. High impedance CMOS input. 1.8V to 3.3V logic. Active HIGH device enable.
2	GND	power_in	Ground connection.
3	BIASVCO	passive	VCO bias. Connect low ESR capacitor in 0.47µF to 4.7µF range to ground; 0.47µF for faster calibration, 4.7µF for better in-band phase noise.
4	GND	power_in	Ground connection.
5	PSYNC	input	Phase sync input with configurable signal level. Connect 100Ω series resistor to PSYNC signal, or to GND if not used.
6	GND	power_in	Ground connection.
7	VCCDIG	power_in	Digital power supply. Connect to 3.3V, add low ESR 0.1µF and 1µF decoupling capacitors to ground.
8	OSCIN_P	input	Reference input clock (+). High impedance self-biasing pin. AC coupling required. If unused, AC couple through 50Ω resistor to ground.
9	OSCIN_N	input	Reference input clock (-). High impedance self-biasing pin. AC coupling required. If unused, AC couple through 50Ω resistor to ground.
10	REGIN	passive	Input reference path regulator decoupling. Connect 1µF decoupling capacitor to ground close to pin; recommend additional low ESR 0.1µF decoupling capacitor for high frequency noise filtering.
11	SRREQ_P	input	Differential SYSREF input clock (+). Supports AC and DC coupling.
12	SRREQ_N	input	Differential SYSREF input clock (-). Supports AC and DC coupling.
13	VCCCP	power_in	Charge pump power supply. Connect to 3.3V, add 1µF decoupling capacitor to ground.
14	CPOUT	output	Charge pump output. Recommend placing loop filter C1 capacitor close to this pin.
15	GND	power_in	Ground connection.
16	GND	power_in	Ground connection.
17	VCCMASH	power_in	Digital power supply for Σ-Δ modulator. Connect to 3.3V, add low ESR 0.1µF and 1µF decoupling capacitors to ground.
18	SCK	input	SPI clock. High impedance CMOS input. 1.8V to 3.3V logic.
19	SDI	input	SPI data. High impedance CMOS input. 1.8V to 3.3V logic.
20	PFDIN	input	External PFD input. Self-biasing pin. AC coupling and external 50Ω resistor to ground required.
21	SROUT_P	output	Differential SYSREF output (+). Internal 50Ω pull-up.
22	SROUT_N	output	Differential SYSREF output (-). Internal 50Ω pull-up.
23	MUXOUT	output	SPI readback output. 3.3V logic. High impedance when CE = LOW.
24	VCCBUF	power_in	Output buffer power supply. Connect to 3.3V, add low ESR 0.1µF and 1µF decoupling capacitors to ground.
25	RFOUTB_N	output	Differential output B (-). Internal 50Ω pull-up. AC coupling required.
26	RFOUTB_P	output	Differential output B (+). Internal 50Ω pull-up. AC coupling required.
27	GND	power_in	Ground connection.
28	RFIN	input	External VCO input. Internal 50Ω termination. AC coupling required.
29	GND	power_in	Ground connection.
30	RFOUTA_N	output	Differential output A (-). Internal 50Ω pull-up. AC coupling required.
31	RFOUTA_P	output	Differential output A (+). Internal 50Ω pull-up. AC coupling required.
32	GND	power_in	Ground connection.
33	VCCBUF2	power_in	Buffer power supply. Connect to 3.3V, add low ESR 0.1µF and 1µF decoupling capacitors to ground.
34	BIASVCO2	passive	VCO bias. Connect 1µF decoupling capacitor to ground, placed close to pin.
35	NC	unconnected	No connection. Pin can be grounded or left unconnected.
36	REFVCO2	passive	VCO power supply reference. Connect 1µF decoupling capacitor to ground.
37	MUTE	input	Buffer mute control. High impedance CMOS input. 1.8V to 3.3V logic.
38	LD	output	Lock detection output. 3.3V logic.
39	CS#	input	SPI latch. High impedance CMOS input. 1.8V to 3.3V logic.
40	GND	power_in	Ground connection.
41	BIASVAR	passive	VCO varactor bias. Connect 1µF decoupling capacitor to ground.
42	GND	power_in	Ground connection.
43	VTUNE	input	VCO tuning voltage input. Connect capacitor ≥1.5nF to VCO ground.
44	REFVCO	passive	VCO power supply reference. Connect 10µF decoupling capacitor to ground.
45	VCCVCO	power_in	VCO power supply. Connect to 3.3V, add low ESR 0.1µF and 1µF decoupling capacitors to ground.
46	REGVCO	passive	VCO regulator node. Connect 1µF decoupling capacitor to ground.
47	GND	power_in	Ground connection.
48	GND	power_in	Ground connection.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-48(7x7)
Category	Clock/Timing
Pins	49

CAD (KiCad official)

Symbol: LMX2820RTCR
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48(7x7) (KiCad packages3D, STEP)
3D model files: lmx2820rtcr-etched.step / lmx2820rtcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmx2820rtcr.step / lmx2820rtcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (42 pp, sha256 68ac37bbe6ee37a2, retrieved 2026-10-03, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF