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LMX2531LQ1742

Public Made by Adom

by adom

Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, WQFN-36(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LMX2531LQ1742

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · WQFN-36(6x6)

LMX2531LQ1742 from Texas Instruments, in a WQFN-36(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VccDIG power_in Power supply for the digital LDO circuitry, input range 2.8 V to 3.2 V, with bypass capacitors placed as close as possible to the pin.
2 NC unconnected No connect.
3 GND power_in Ground.
4 NC unconnected No connect.
5 NC unconnected No connect.
6 VregBUF power_out Internally regulated voltage for the VCO buffer circuitry; connect to ground with a capacitor.
7 NC unconnected No connect.
8 DATA input MICROWIRE serial data input (high-impedance CMOS) that must not exceed 2.75 V; data is clocked in MSB first and the last bits form the control or register select bits.
9 CLK input MICROWIRE clock input (high-impedance CMOS) that must not exceed 2.75 V; data is clocked into the shift register on the rising edge.
10 LE input MICROWIRE latch enable input (high-impedance CMOS) that must not exceed 2.75 V; data in the shift register is loaded into the selected latch when LE goes high.
11 CE input Chip enable input (high-impedance CMOS) that must not exceed 2.75 V; bringing CE high powers up the device.
12 NC unconnected No connect.
13 NC unconnected No connect.
14 NC unconnected No connect; do NOT ground this pin or the pad above it.
15 NC unconnected No connect; do NOT ground this pin or the pad above it.
16 VccVCO power_in Power supply for the VCO regulator circuitry, input range 2.8 V to 3.2 V, with bypass capacitors placed as close as possible to the pin.
17 VregVCO power_out Internally regulated voltage for the VCO circuitry, not intended to drive an external load; connect to ground with a capacitor and some series resistance.
18 VrefVCO passive Internal reference voltage for the VCO LDO, not intended to drive an external load; connect to ground with a capacitor.
19 GND power_in Ground for the VCO circuitry.
20 GND power_in Ground for the VCO output buffer circuitry.
21 Fout output Buffered RF output for the VCO.
22 VccBUF power_in Power supply for the VCO buffer circuitry, input range 2.8 V to 3.2 V, with bypass capacitors placed as close as possible to the pin.
23 Vtune input VCO tuning voltage input, connected to CPout through an external passive loop filter.
24 CPout output PLL charge pump output, connected to Vtune through an external passive loop filter.
25 FLout output Open-drain NMOS output used for FastLock or as a general-purpose output; a pull-up resistor is required when used open-drain.
26 VregPLL1 power_out Internally regulated voltage for the PLL charge pump, not intended to drive an external load; connect to ground with a capacitor.
27 VccPLL power_in Power supply for the PLL, input range 2.8 V to 3.2 V, with bypass capacitors placed as close as possible to the pin.
28 VregPLL2 power_out Internally regulated voltage for the RF digital circuitry, not intended to drive an external load; connect to ground with a capacitor.
29 NC unconnected No connect.
30 Ftest/LD output Multiplexed CMOS output used to monitor PLL lock condition or for diagnostics; its output levels are set by VOH and VOL, not by the supply voltage.
31 OSCin input Oscillator input.
32 OSCin* input Complementary oscillator input; when a single-ended source is used, a bypass capacitor should be placed as close as possible to this pin and connected to ground.
33 Test output Test pin for test purposes that must be grounded for normal operation.
34 GND power_in Ground.
35 NC unconnected No connect.
36 VregDIG power_out Internally regulated voltage for the digital LDO circuitry, connected to ground with a capacitor.
37 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-36(6x6)
Category Clock/Timing
Pins 37

CAD (KiCad official)

  • Symbol: LMX2531LQ1742
  • Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
  • 3D model: WQFN-36(6x6) (KiCad packages3D, STEP)
  • 3D model files: lmx2531lq1742-etched.step / lmx2531lq1742-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmx2531lq1742.step / lmx2531lq1742.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (47 pp, sha256 640d071469707184, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF