component
LMX2531LQ1146E
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, WQFN-36(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+73@@ -0,0 +1,73 @@+# LMX2531LQ1146E++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · WQFN-36(6x6)++LMX2531LQ1146E from Texas Instruments, in a WQFN-36(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VccDIG | power_in | Power supply for the digital LDO circuitry; input may range from 2.8 to 3.2 V, with bypass capacitors placed as close as possible to the pin and ground. |+| 2 | NC | unconnected | No connect pin; the datasheet notes there is no advantage to grounding it. |+| 3 | GND | power_in | Ground. |+| 4 | NC | unconnected | No connect pin; the datasheet notes there is no advantage to grounding it. |+| 5 | NC | unconnected | No connect pin; the datasheet notes there is no advantage to grounding it. |+| 6 | VregBUF | power_out | Internally regulated voltage for the VCO buffer circuitry; connect to ground with a capacitor. |+| 7 | NC | unconnected | No connect pin; the datasheet notes there is no advantage to grounding it. |+| 8 | DATA | input | MICROWIRE serial data input; high-impedance CMOS input that must not exceed 2.75 V, with data clocked in MSB first. |+| 9 | CLK | input | MICROWIRE clock input; high-impedance CMOS input that must not exceed 2.75 V, with data clocked into the shift register on the rising edge. |+| 10 | LE | input | MICROWIRE latch enable input; high-impedance CMOS input that must not exceed 2.75 V, with shift register data loaded into the selected latch when LE goes HIGH. |+| 11 | CE | input | Chip enable input; high-impedance CMOS input that must not exceed 2.75 V, with the device powered up when CE is high. |+| 12 | NC | unconnected | No connect pin; the datasheet notes there is no advantage to grounding it. |+| 13 | NC | unconnected | No connect pin; the datasheet notes there is no advantage to grounding it. |+| 14 | NC | unconnected | No connect pin that must not be grounded; the datasheet states this also applies to the pad above these pins. |+| 15 | NC | unconnected | No connect pin that must not be grounded; the datasheet states this also applies to the pad above these pins. |+| 16 | VccVCO | power_in | Power supply for the VCO regulator circuitry; input may range from 2.8 to 3.2 V, with bypass capacitors placed as close as possible to the pin and ground. |+| 17 | VregVCO | power_out | Internally regulated voltage for the VCO circuitry, not intended to drive an external load; connect to ground with a capacitor and some series resistance. |+| 18 | VrefVCO | power_out | Internal reference voltage for the VCO LDO, not intended to drive an external load; connect to ground with a capacitor. |+| 19 | GND | power_in | Ground for the VCO circuitry. |+| 20 | GND | power_in | Ground for the VCO output buffer circuitry. |+| 21 | Fout | output | Buffered RF output for the VCO. |+| 22 | VccBUF | power_in | Power supply for the VCO buffer circuitry; input may range from 2.8 to 3.2 V, with bypass capacitors placed as close as possible to the pin and ground. |+| 23 | Vtune | input | Tuning voltage input for the VCO, connected to the CPout pin through an external passive loop filter. |+| 24 | CPout | output | Charge pump output for the PLL, connected to Vtune through an external passive loop filter. |+| 25 | FLout | output | Open-drain NMOS output used for FastLock or as a general-purpose output. |+| 26 | VregPLL1 | power_out | Internally regulated voltage for the PLL charge pump, not intended to drive an external load; connect to ground with a capacitor. |+| 27 | VccPLL | power_in | Power supply for the PLL; input may range from 2.8 to 3.2 V, with bypass capacitors placed as close as possible to the pin and ground. |+| 28 | VregPLL2 | power_out | Internally regulated voltage for the RF digital circuitry, not intended to drive an external load; connect to ground with a capacitor. |+| 29 | NC | unconnected | No connect pin; the datasheet notes there is no advantage to grounding it. |+| 30 | Ftest/LD | output | Multiplexed CMOS output typically used to monitor PLL lock condition; its output levels are set by VOH and VOL, not by the supply voltage. |+| 31 | OSCin | input | Oscillator input. |+| 32 | OSCin* | input | Complementary oscillator input; when a single-ended source is used, a bypass capacitor should be placed as close as possible to this pin and connected to ground. |+| 33 | Test | output | Test pin that should be grounded for normal operation. |+| 34 | GND | power_in | Ground. |+| 35 | NC | unconnected | No connect pin; the datasheet notes there is no advantage to grounding it. |+| 36 | VregDIG | power_out | Internally regulated voltage for the LDO digital circuitry; a 10 nF bypass capacitor is recommended. |+| 37 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-36(6x6) |+| Category | Clock/Timing |+| Pins | 37 |++## CAD (KiCad official)++- Symbol: `LMX2531LQ1146E`+- Footprint: `Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm`+- 3D model: WQFN-36(6x6) (KiCad packages3D, STEP)+- 3D model files: `lmx2531lq1146e-etched.step` / `lmx2531lq1146e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmx2531lq1146e.step` / `lmx2531lq1146e.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lmx2531) (47 pp, sha256 `640d071469707184`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lmx2531lq1146e-datasheet.pdf)
page.jsonadded+372@@ -0,0 +1,372 @@+{+ "slug": "lmx2531lq1146e",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, WQFN-36(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "lmx2531lq1146e",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lmx2531lq1146e.kicad_sym",+ "lmx2531lq1146e.kicad_mod",+ "lmx2531lq1146e.glb",+ "lmx2531lq1146e.step",+ "lmx2531lq1146e.lbr",+ "docs/hero.png",+ "docs/lmx2531lq1146e-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lmx2531lq1146e-hero.glb",+ "lmx2531lq1146e-hero.overlay.json"+ ],+ "component": {+ "mpn": "LMX2531LQ1146E",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-36(6x6)",+ "pin_count": 37,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/lmx2531",+ "parts": {+ "symbol": "lmx2531lq1146e.kicad_sym",+ "footprint": "lmx2531lq1146e.kicad_mod",+ "model_3d": "lmx2531lq1146e-hero.glb",+ "model_3d_plain": "lmx2531lq1146e.glb",+ "model_3d_step": "lmx2531lq1146e-etched.step",+ "model_3d_step_plain": "lmx2531lq1146e.step",+ "lbr": "lmx2531lq1146e.lbr"+ },+ "distributor_links": {+ "lcsc": "C2662644"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:51:59Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VccDIG",+ "type": "power_in",+ "description": "Power supply for the digital LDO circuitry; input may range from 2.8 to 3.2 V, with bypass capacitors placed as close as possible to the pin and ground."+ },+ {+ "number": "2",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; the datasheet notes there is no advantage to grounding it."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "4",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; the datasheet notes there is no advantage to grounding it."+ },+ {+ "number": "5",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; the datasheet notes there is no advantage to grounding it."+ },+ {+ "number": "6",+ "name": "VregBUF",+ "type": "power_out",+ "description": "Internally regulated voltage for the VCO buffer circuitry; connect to ground with a capacitor."+ },+ {+ "number": "7",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; the datasheet notes there is no advantage to grounding it."+ },+ {+ "number": "8",+ "name": "DATA",+ "type": "input",+ "description": "MICROWIRE serial data input; high-impedance CMOS input that must not exceed 2.75 V, with data clocked in MSB first."+ },+ {+ "number": "9",+ "name": "CLK",+ "type": "input",+ "description": "MICROWIRE clock input; high-impedance CMOS input that must not exceed 2.75 V, with data clocked into the shift register on the rising edge."+ },+ {+ "number": "10",+ "name": "LE",+ "type": "input",+ "description": "MICROWIRE latch enable input; high-impedance CMOS input that must not exceed 2.75 V, with shift register data loaded into the selected latch when LE goes HIGH."+ },+ {+ "number": "11",+ "name": "CE",+ "type": "input",+ "description": "Chip enable input; high-impedance CMOS input that must not exceed 2.75 V, with the device powered up when CE is high."+ },+ {+ "number": "12",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; the datasheet notes there is no advantage to grounding it."+ },+ {+ "number": "13",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; the datasheet notes there is no advantage to grounding it."+ },+ {+ "number": "14",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin that must not be grounded; the datasheet states this also applies to the pad above these pins."+ },+ {+ "number": "15",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin that must not be grounded; the datasheet states this also applies to the pad above these pins."+ },+ {+ "number": "16",+ "name": "VccVCO",+ "type": "power_in",+ "description": "Power supply for the VCO regulator circuitry; input may range from 2.8 to 3.2 V, with bypass capacitors placed as close as possible to the pin and ground."+ },+ {+ "number": "17",+ "name": "VregVCO",+ "type": "power_out",+ "description": "Internally regulated voltage for the VCO circuitry, not intended to drive an external load; connect to ground with a capacitor and some series resistance."+ },+ {+ "number": "18",+ "name": "VrefVCO",+ "type": "power_out",+ "description": "Internal reference voltage for the VCO LDO, not intended to drive an external load; connect to ground with a capacitor."+ },+ {+ "number": "19",+ "name": "GND",+ "type": "power_in",+ "description": "Ground for the VCO circuitry."+ },+ {+ "number": "20",+ "name": "GND",+ "type": "power_in",+ "description": "Ground for the VCO output buffer circuitry."+ },+ {+ "number": "21",+ "name": "Fout",+ "type": "output",+ "description": "Buffered RF output for the VCO."+ },+ {+ "number": "22",+ "name": "VccBUF",+ "type": "power_in",+ "description": "Power supply for the VCO buffer circuitry; input may range from 2.8 to 3.2 V, with bypass capacitors placed as close as possible to the pin and ground."+ },+ {+ "number": "23",+ "name": "Vtune",+ "type": "input",+ "description": "Tuning voltage input for the VCO, connected to the CPout pin through an external passive loop filter."+ },+ {+ "number": "24",+ "name": "CPout",+ "type": "output",+ "description": "Charge pump output for the PLL, connected to Vtune through an external passive loop filter."+ },+ {+ "number": "25",+ "name": "FLout",+ "type": "output",+ "description": "Open-drain NMOS output used for FastLock or as a general-purpose output."+ },+ {+ "number": "26",+ "name": "VregPLL1",+ "type": "power_out",+ "description": "Internally regulated voltage for the PLL charge pump, not intended to drive an external load; connect to ground with a capacitor."+ },+ {+ "number": "27",+ "name": "VccPLL",+ "type": "power_in",+ "description": "Power supply for the PLL; input may range from 2.8 to 3.2 V, with bypass capacitors placed as close as possible to the pin and ground."+ },+ {+ "number": "28",+ "name": "VregPLL2",+ "type": "power_out",+ "description": "Internally regulated voltage for the RF digital circuitry, not intended to drive an external load; connect to ground with a capacitor."+ },+ {+ "number": "29",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; the datasheet notes there is no advantage to grounding it."+ },+ {+ "number": "30",+ "name": "Ftest/LD",+ "type": "output",+ "description": "Multiplexed CMOS output typically used to monitor PLL lock condition; its output levels are set by VOH and VOL, not by the supply voltage."+ },+ {+ "number": "31",+ "name": "OSCin",+ "type": "input",+ "description": "Oscillator input."+ },+ {+ "number": "32",+ "name": "OSCin*",+ "type": "input",+ "description": "Complementary oscillator input; when a single-ended source is used, a bypass capacitor should be placed as close as possible to this pin and connected to ground."+ },+ {+ "number": "33",+ "name": "Test",+ "type": "output",+ "description": "Test pin that should be grounded for normal operation."+ },+ {+ "number": "34",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "35",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect pin; the datasheet notes there is no advantage to grounding it."+ },+ {+ "number": "36",+ "name": "VregDIG",+ "type": "power_out",+ "description": "Internally regulated voltage for the LDO digital circuitry; a 10 nF bypass capacitor is recommended."+ },+ {+ "number": "37",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The Pin Configuration drawing text is garbled in the extract, so pin numbers were taken from the Pin; The datasheet assigns LMX2531LQ1146E to the NJH0036D (D version) package drawing; the NJG0036A (A ve; The exposed die attach pad (DAP) is referenced in the Do's and Don'ts section as grounded but has no",+ "exposed pad 37 added from the footprint"+ ],+ "pages_sent": 16,+ "cost_usd": 0.1256,+ "at": "2026-10-08T15:51:40"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lmx2531",+ "pages": 47,+ "sha256": "640d071469707184",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 37,+ "described": 37,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lmx2531lq1146e.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "6212c4fd2463ccb7c6ae2c35f5e24c80884153fcaeaf8e86549c0e49087bc8bb",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lmx2531lq1146e-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "5883bf16fbefc70df04e39d023fd66e3605fb69aa9585faddc877ac213c86274",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}