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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LMX2531LQ1146E

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · WQFN-36(6x6)

LMX2531LQ1146E from Texas Instruments, in a WQFN-36(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VccDIG	power_in	Power supply for the digital LDO circuitry; input may range from 2.8 to 3.2 V, with bypass capacitors placed as close as possible to the pin and ground.
2	NC	unconnected	No connect pin; the datasheet notes there is no advantage to grounding it.
3	GND	power_in	Ground.
4	NC	unconnected	No connect pin; the datasheet notes there is no advantage to grounding it.
5	NC	unconnected	No connect pin; the datasheet notes there is no advantage to grounding it.
6	VregBUF	power_out	Internally regulated voltage for the VCO buffer circuitry; connect to ground with a capacitor.
7	NC	unconnected	No connect pin; the datasheet notes there is no advantage to grounding it.
8	DATA	input	MICROWIRE serial data input; high-impedance CMOS input that must not exceed 2.75 V, with data clocked in MSB first.
9	CLK	input	MICROWIRE clock input; high-impedance CMOS input that must not exceed 2.75 V, with data clocked into the shift register on the rising edge.
10	LE	input	MICROWIRE latch enable input; high-impedance CMOS input that must not exceed 2.75 V, with shift register data loaded into the selected latch when LE goes HIGH.
11	CE	input	Chip enable input; high-impedance CMOS input that must not exceed 2.75 V, with the device powered up when CE is high.
12	NC	unconnected	No connect pin; the datasheet notes there is no advantage to grounding it.
13	NC	unconnected	No connect pin; the datasheet notes there is no advantage to grounding it.
14	NC	unconnected	No connect pin that must not be grounded; the datasheet states this also applies to the pad above these pins.
15	NC	unconnected	No connect pin that must not be grounded; the datasheet states this also applies to the pad above these pins.
16	VccVCO	power_in	Power supply for the VCO regulator circuitry; input may range from 2.8 to 3.2 V, with bypass capacitors placed as close as possible to the pin and ground.
17	VregVCO	power_out	Internally regulated voltage for the VCO circuitry, not intended to drive an external load; connect to ground with a capacitor and some series resistance.
18	VrefVCO	power_out	Internal reference voltage for the VCO LDO, not intended to drive an external load; connect to ground with a capacitor.
19	GND	power_in	Ground for the VCO circuitry.
20	GND	power_in	Ground for the VCO output buffer circuitry.
21	Fout	output	Buffered RF output for the VCO.
22	VccBUF	power_in	Power supply for the VCO buffer circuitry; input may range from 2.8 to 3.2 V, with bypass capacitors placed as close as possible to the pin and ground.
23	Vtune	input	Tuning voltage input for the VCO, connected to the CPout pin through an external passive loop filter.
24	CPout	output	Charge pump output for the PLL, connected to Vtune through an external passive loop filter.
25	FLout	output	Open-drain NMOS output used for FastLock or as a general-purpose output.
26	VregPLL1	power_out	Internally regulated voltage for the PLL charge pump, not intended to drive an external load; connect to ground with a capacitor.
27	VccPLL	power_in	Power supply for the PLL; input may range from 2.8 to 3.2 V, with bypass capacitors placed as close as possible to the pin and ground.
28	VregPLL2	power_out	Internally regulated voltage for the RF digital circuitry, not intended to drive an external load; connect to ground with a capacitor.
29	NC	unconnected	No connect pin; the datasheet notes there is no advantage to grounding it.
30	Ftest/LD	output	Multiplexed CMOS output typically used to monitor PLL lock condition; its output levels are set by VOH and VOL, not by the supply voltage.
31	OSCin	input	Oscillator input.
32	OSCin*	input	Complementary oscillator input; when a single-ended source is used, a bypass capacitor should be placed as close as possible to this pin and connected to ground.
33	Test	output	Test pin that should be grounded for normal operation.
34	GND	power_in	Ground.
35	NC	unconnected	No connect pin; the datasheet notes there is no advantage to grounding it.
36	VregDIG	power_out	Internally regulated voltage for the LDO digital circuitry; a 10 nF bypass capacitor is recommended.
37	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-36(6x6)
Category	Clock/Timing
Pins	37

CAD (KiCad official)

Symbol: LMX2531LQ1146E
Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
3D model: WQFN-36(6x6) (KiCad packages3D, STEP)
3D model files: lmx2531lq1146e-etched.step / lmx2531lq1146e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmx2531lq1146e.step / lmx2531lq1146e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (47 pp, sha256 640d071469707184, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF