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lmv824idrg-etched.glb lmv824idrg: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 1d ago
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README.md lmv824idrg: specified limits as data (metadata.characteristics, 34 rows from the datasheet) · Ray 21d ago

LMV824IDRG

HANSCHIP semiconductor · Operational Amplifier · SOP-14

LMV824IDRG from HANSCHIP semiconductor, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUTA output Output of op-amp channel A. Rail-to-rail output stage.
2 -INA input Inverting input of op-amp channel A.
3 +INA input Non-inverting input of op-amp channel A.
4 V+ power_in Positive supply voltage, 2.7V to 5.5V single supply (or ±1.35V to ±2.75V dual).
5 +INB input Non-inverting input of op-amp channel B.
6 -INB input Inverting input of op-amp channel B.
7 OUTB output Output of op-amp channel B. Rail-to-rail output stage.
8 OUTC output Output of op-amp channel C. Rail-to-rail output stage.
9 -INC input Inverting input of op-amp channel C.
10 +INC input Non-inverting input of op-amp channel C.
11 V- power_in Negative supply / ground. Tie to GND for single-supply operation.
12 +IND input Non-inverting input of op-amp channel D.
13 -IND input Inverting input of op-amp channel D.
14 OUTD output Output of op-amp channel D. Rail-to-rail output stage.

Key specifications

Parameter Value
Manufacturer HANSCHIP semiconductor
Package SOP-14
Category Op-amp/Cmp
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • LMV824IDRG
  • LMV824IDRGIPWR
  • LMV824IDRGIPW

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Offset Voltage (VOS) VOS 0.8 3.5 mV TA = +25°C (Vs=5V, VCM=VS/2, RL=600Ω per table) 3
Input Offset Voltage (VOS) VOS 0.8 3.9 mV TA = 0°C to 70°C 3
Input Offset Voltage (VOS) VOS 0.8 4.3 mV TA = -40°C to 85°C 3
Input Offset Voltage (VOS) VOS 0.8 4.6 mV TA = -40°C to 125°C 3
Common Mode Rejection Ratio (CMRR) CMRR 73 90 dB VS = 5.5V, VCM = -0.1V to 4V; TA = +25°C 3
Common Mode Rejection Ratio (CMRR) CMRR 70 90 dB VS = 5.5V, VCM = -0.1V to 4V; TA = 0°C to 70°C 3
Common Mode Rejection Ratio (CMRR) CMRR 65 90 dB VS = 5.5V, VCM = -0.1V to 4V; TA = -40°C to 125°C 3
Common Mode Rejection Ratio (CMRR) CMRR 83 dB VS = 5.5V, VCM = -0.1V to 5.6V 3
Open-Loop Voltage Gain (AOL) AOL 90 97 dB RL = 600Ω, VO = 0.15V to 4.85V; TA = +25°C 3
Open-Loop Voltage Gain (AOL) AOL 87 97 dB RL = 600Ω, VO = 0.15V to 4.85V; TA = 0°C to 70°C 3
Open-Loop Voltage Gain (AOL) AOL 86 97 dB RL = 600Ω, VO = 0.15V to 4.85V; TA = -40°C to 85°C 3
Open-Loop Voltage Gain (AOL) AOL 79 97 dB RL = 600Ω, VO = 0.15V to 4.85V; TA = -40°C to 125°C 3
Open-Loop Voltage Gain (AOL) AOL 108 dB RL = 10kΩ, VO = 0.05V to 4.95V 3
Output Current (IOUT) IOUT 49 53 mA TA = +25°C 3
Output Current (IOUT) IOUT 45 53 mA TA = 0°C to 70°C 3
Output Current (IOUT) IOUT 40 53 mA TA = -40°C to 85°C 3
Output Current (IOUT) IOUT 35 53 mA TA = -40°C to 125°C 3
Power Supply Rejection Ratio (PSRR) PSRR 74 91 dBµA VS = +2.5V to +5.5V, VCM = (-VS) + 0.5V, IOUT = 0; TA = +25°C 3
Power Supply Rejection Ratio (PSRR) PSRR 72 91 dBµA VS = +2.5V to +5.5V, VCM = (-VS) + 0.5V, IOUT = 0; TA = 0°C to 70°C 3
Power Supply Rejection Ratio (PSRR) PSRR 68 91 dBµA VS = +2.5V to +5.5V, VCM = (-VS) + 0.5V, IOUT = 0; TA = -40°C to 125°C 3
Quiescent Current per Amplifier (IQ) IQ 470 650 dBµA VS = +2.5V to +5.5V, VCM = (-VS) + 0.5V, IOUT = 0; TA = +25°C 3
Quiescent Current per Amplifier (IQ) IQ 470 727 dBµA VS = +2.5V to +5.5V, VCM = (-VS) + 0.5V, IOUT = 0; TA = 0°C to 70°C 3
Quiescent Current per Amplifier (IQ) IQ 470 750 dBµA VS = +2.5V to +5.5V, VCM = (-VS) + 0.5V, IOUT = 0; TA = -40°C to 85°C 3
Quiescent Current per Amplifier (IQ) IQ 470 815 dBµA VS = +2.5V to +5.5V, VCM = (-VS) + 0.5V, IOUT = 0; TA = -40°C to 125°C 3
Operating Voltage Range 2.1 5.5 V TA = +25°C 3
Power Supply Voltage (VDD to Vss) -0.5 7.5 V 2
Analog Input Voltage (IN+ or IN-) -0.5 0.5 V Printed as min Vss-0.5V and max VDD+0.5V (offsets relative to supply rails) 2
PDB Input Voltage -0.5 7 V Printed as min Vss-0.5V (offset relative to Vss) 2
Operating Temperature Range -40 125 °C 2
Junction Temperature 160 °C 2
Storage Temperature Range -55 150 °C 2
Lead Temperature (soldering) 260 °C soldering, 10 sec 2
ESD Susceptibility HBM 8 KV HBM 2
ESD Susceptibility MM 400 V MM 2

CAD (KiCad official)

  • Symbol: LMV824IDRG
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: lmv824idrg-etched.step / lmv824idrg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmv824idrg.step / lmv824idrg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HANSCHIP semiconductor datasheet (14 pp, sha256 528cb0ff330f359f, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF